参数资料
型号: XR17V354IB176-F
厂商: Exar Corporation
文件页数: 56/66页
文件大小: 0K
描述: IC UART PCIE 256B QUAD 176FPBGA
产品培训模块: PCIe UARTs
标准包装: 160
特点: *
通道数: 4,QUART
FIFO's: 256 字节
规程: RS485
电源电压: 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 176-LFBGA
供应商设备封装: 176-FPBGA(13x13)
包装: 托盘
其它名称: 1016-1472
XR17V354IB176-F-ND
XR17V354
6
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
MPIO10
P1
I/O
Multi-purpose input/output 10. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO11
M3
I/O
Multi-purpose input/output 11. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO12
N2
I/O
Multi-purpose input/output 12. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO13
P2
I/O
Multi-purpose input/output 13. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO14
M4
I/O
Multi-purpose input/output 14. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO15
N3
I/O
Multi-purpose input/output 15. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
EEPROM SIGNALS
EECK
P13
O
Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for
reading the vendor and sub-vendor ID during power up or reset. However, it
can be manually clocked thru the Configuration Register REGB.
EECS
R14
O
Chip select to a EEPROM device like 93C46. It is manually selectable thru
the Configuration Register REGB. Requires a pull-up 4.7K ohm resistor for
external sensing of EEPROM during power up.
EEDI
P14
O
Write data to EEPROM device. It is manually accessible thru the Configura-
tion Register REGB.
EEDO
M12
I
Read data from EEPROM device. It is manually accessible thru the Configu-
ration Register REGB.
JTAG SIGNALS
TRST#
N4
I
JTAG Test Reset. This signal is active LOW.
TCK
P3
I
JTAG Test Clock
TMS
M5
I
JTAG Test Mode Select
TDI
R3
I
JTAG Data Input
TDO
P4
O
JTAG Data Output
BUCK REGULATOR SIGNALS
ENABLE
C14
I
Connect to VCC to enable buck regulator. Connect to GND to disable buck
regulator.
LX
A13
A14
O
Connect these two signals together to external 4.7uH inductor.
FB
C11
I
Connect this signal to other end of external 4.7uH inductor. 47uF capacitor to
GND is also required on this pin.
PWRGD
D13
O
Indicates that 1.2V core has been powered up.
ANCILLARY SIGNALS
RESET#
R2
I
System reset (active low). In normal operation, this signal should be HIGH.
PIN DESCRIPTIONS
NAME
PIN #TYPE
DESCRIPTION
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