参数资料
型号: XR20M1172IG28
厂商: Exar Corporation
文件页数: 6/55页
文件大小: 0K
描述: IC UART FIFO I2C/SPI 64B 28TSSOP
产品变化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
标准包装: 50
特点: *
通道数: 2,DUART
FIFO's: 64 字节
规程: RS485
电源电压: 1.62 V ~ 3.63 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
XR20M1172
14
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a
multiple of 4.
When using a non-standard data rate crystal or external clock, the divisor value can be
calculated with the following equation(s):
The closest divisor that is obtainable in the M1172 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode,
DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode,
DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode,
DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
FIGURE 12. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
Fractional Baud
Rate Generator
Logic
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