参数资料
| 型号： | XRD9816BCV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 13/53页 |
| 文件大小： | 0K |
| 描述： | IC 16BIT CCD/CIS SIG PROC 48TQFP |
| 标准包装： | 250 |
| 位数： | 16 |
| 通道数： | 3 |
| 电压 - 电源，模拟： | 4.5 V ~ 5.5 V |
| 电压 - 电源，数字： | 3 V ~ 5.5 V |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
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XRD9814B/9816B
20
Rev. 1.00
Maximum Capacitance (CDS Pixel Mode)
Limitation #1
Since the black level is clamped during each pixel
period the input bias current contributes an insignifi-
cant amount of droop during one pixel period. However,
pixel-pixel variations in the black level may appear as
errors . For a worst case gain of -10, 2V A/D FSR and
14-bit accuracy, one lsb of
error corresponds to
12.5uV input-referred. Assuming 1mV of pixel-pixel
variation in the black level, the maximumcoupling
capacitor can be determined as a function of the
clamping period and internal clamp resistance.
where tpwb=clamp pulse width (BSAMP)
Rc=Clamp resistance
Rs=Signal source-resistance
For typical values of tpwb=65ns, Rc=100
, Rs=50,
C
MAX ≤100pF.
Limitation #2
The maximum input capacitance may also be limited
by the time allowed to charge the input capacitor to the
difference between the black level and clamp levels.
The capacitor value can be related to the number of
clamp pulses allowed before the capacitor voltage
settles to within the desired accuracy.
where tpwb = clamp pulse width (BSAMP)
N
= number of pixels allowed to settle
Rc = clamp resistance
Rs = signal source-resistance
Vr = black level
Vc = XRD9814B/9816B clamp voltage
V
ε = error voltage
Assuming that Vr=5V, Vc=4V, V
ε=12.5uV, Rc=100,
Rs=50
, tpwb=65ns and N=10 the maximum allow-
able input capacitor is equal to 384pF. In this case the
input capacitance is limited by pixel-pixel changes in
the black level (first calculation).
Minimum Capacitance (CDS Pixel Mode)
The minimum coupling capacitance is limited by para-
sitic effects including pin and board capacitance. A
minimum value of 68pF is recommended.
Maximum Capacitance (CDS Line Mode)
Since the coupling capacitor is charged only at the
beginning of each line and not clamped at each pixel,
the pixel-pixel variation in the black level has no effect
on the capacitor size. The maximum size will be limited
by the number of clamp pulses, clamp pulse-width and
number of lines allowed to charge to a given accuracy.
where tpwb = clamp pulse width (BSAMP)
N
= number of pixels allowed to settle
Rc = clamp resistance
Rs = signal source-resistance
Vr = black level
Vc = XRD9814B/9816B clamp voltage
V
ε = error voltage
Assuming that Vr=5V, Vc=4V, Ve=12.5uV, Rc=100
,
Rs=500
,tpwb=65nsandN=10,the maximumallow-
able input capacitor is equal to 767pF.
If it is desired to settle within one line (L=1) for a given
capacitor value, the number of clamp pulses or the
clamp pulse-width must be increased using the above
equation.
(
)
C
tpwb
Rc
Rs
mV
V
max
ln
=
+
1
12.5
(
)
C
tpwb N
Rc
Rs
Vr
Vc
V
max
ln
=
+
ε
(
)
C
N L tpwb
Rc
Rs
Vr
Vc
V
max
ln
=
+
ε
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