参数资料
| 型号： | XRT71D04IVTR |
| 厂商： | Exar Corporation |
| 文件页数： | 1/22页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATTENUATOR 4CH 80TQFP |
| 标准包装： | 1,000 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 4:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 44.736MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.135 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-TQFP（14x14） |
| 包装： | 带卷 (TR) |
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
APRIL 2001
REV. 1.1.1
GENERAL DESCRIPTION
The XRT71D04 is a four channel, single chip Jitter At-
tenuator, that meets the Jitter transfer characteristic
requirements specified in the ETSI TBR-24, Bellcore
GR-499 and GR-253 standards.
In addition, the XRT71D04 also meets the Jitter and
Wander specifications described in the ANSI
T1.105.03b 1997, Bellcore GR-253 and GR-499 stan-
dards for Desynchronizing and Pointer adjustments in
the DS3 to STS-SPE mapping applications.
FEATURES
Meets the E3/DS3/STS-1 jitter requirements
No external components required
Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-499-CORE,1995
GR-253-CORE standards
Meets output jitter requirement as specified by
ETSI TBR24
Meets the Jitter and Wander specifications
described in T1.105.03b,GR-253 and GR-499 stan-
dards
Selectable buffer size of 16 and 32 bits
Jitter attenuator can be disabled
Available in a 80 pin TQFP package
Single 3.3V or 5.0V supply.
Operates over - 400 C to 850 C temperature range.
APPLICATIONS
E3/DS3 Access Equipment
STS-SPE to DS3 Mapper
DSLAMs
FIGURE 1. BLOCK DIAGRAM (ONE CHANNEL)
DS3/E3_n
Microprocessor Serial
Interface
HOST
Reset
XRT71D04
n = 0, 1, 2, 3
16/32 Bit FIFO
Timing Control Block /
Phase locked Loop
Write Clock
Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
DJA_n
RClk_n
RClkES
RPOS_n
RNEG_n
FSS
MCLK_n
STS1_n
Channel 0
Channel 1
Channel 2
Channel 3
ICT
CS
SDI
SDO SClk
MODE_CTRL
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