参数资料
型号: XRT83SL28IV-F
厂商: Exar Corporation
文件页数: 8/47页
文件大小: 0K
描述: IC LIU SH E1 8CH 144TQFP
标准包装: 60
类型: 线路接口装置(LIU)
驱动器/接收器数: 8/8
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-TQFP(20x20)
包装: 托盘
XRT83SL28
xr
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
14
1.0 RECEIVE PATH LINE INTERFACE
The receive path of the XRT83SL28 LIU consists of 8 independent E1 receivers. The following section
describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified
block diagram of the receive path is shown in Figure 4.
FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING)
1.1
Internal Termination
The input stage of the receive path accepts standard E1 coaxial cable or E1 twisted pair inputs through RTIP
and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU. This
allows one bill of materials for all modes of operation reducing the number of external components necessary
in system design. The receive termination impedance is selected by programming TERSEL[1:0] to match the
line impedance. The XRT83SL28 has the ability to switch the internal termination to "High" impedance for
redundancy applications. See Redundancy in the Applications Section of this datasheet. Selecting the internal
impedance is shown in Table 1. A typical connection diagram is shown in Figure 5.
FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION
TABLE 1: SELECTING THE INTERNAL IMPEDANCE
TERSEL[1:0]
RECEIVE TERMINATION
0h (00)
75
for Tx and "High-Z" for Rx
1h (01)
120
for Tx and "High-Z" for Rx
2h (10)
75
for Tx and Rx
3h (11)
120
for Tx and Rx
HDB3
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
RCLK
RNEG
RPOS
R
TIP
R
RING
XRT83SL28 LIU
1:1
Internal Impedance
Line Interface E1
One Bill of Materials
Receiver
Input
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