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| 型号： | XRT83SL30IVTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 16/76页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 SGL 64TQFP |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
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XRT83SL30
20
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram.
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes by controlling the TNEG/CODE pin or
the CODE interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in
this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do
not conform to the coding scheme will be reported as Line Code Violation at the RNEG/LCV pin. The length of
the LCV pulse is one RCLK cycle for each code violation. Excessive number of zeros in the receive data
stream is also reported as an error at the same output pin. If AMI decoding is selected in single rail mode,
every bipolar violation in the receive data stream will be reported as an error at the RNEG/LCV pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes. In Host mode, the sampling edge of RCLK output
can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE interface bit, receive
data output at RPOS/RDATA and RNEG/LCV are updated on the falling edge of RCLK. Writing a “0” to the
RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is
available under the control of the RCLKE pin.
FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION
FIGURE 8. RECEIVE CLOCK AND OUTPUT DATA TIMING
Norm alized up to +29dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83SL314 | 制造商:EXAR 制造商全称:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL314_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL314ES | 功能描述:LIN 收发器 14 CHT1/E1 LIUSH RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| XRT83SL314IB | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL314IB-F | 功能描述:LIN 收发器 RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
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