XRT83SL30IVTR-F (Exar) PDF资料下载 Datasheet(37/76 页)

您好，
买卖IC网欢迎您。
请登录
免费注册

您现在的位置：买卖IC网 > PDF目录10009 > XRT83SL30IVTR-F (Exar Corporation)IC LIU T1/E1/J1 SGL 64TQFP PDF资料下载

参数资料

型号：	XRT83SL30IVTR-F
厂商：	Exar Corporation
文件页数：	37/76页
文件大小：	0K
描述：	IC LIU T1/E1/J1 SGL 64TQFP
标准包装：	1,000
类型：	线路接口装置（LIU）
驱动器/接收器数：	1/1
规程：	T1，E1，J1
电源电压：	3.135 V ~ 3.465 V
安装类型：	表面贴装
封装/外壳：	64-LQFP
供应商设备封装：	64-TQFP（10x10）
包装：	带卷 (TR)

XRT83SL30

SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. 1.0.1

DIGITAL LOOP-BACK (DLOOP)

Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the

corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive

data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature

allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is

shown in Figure 21.

DUAL LOOP-BACK

Figure 22 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit

path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the

recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without

passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator

to the RCLK and RPOS/RDATA and RNEG pins.

FIGURE 21. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH

FIGURE 22. SIGNAL FLOW IN DUAL LOOP-BACK MODE

Decoder

Timing

Control

Data &

Clock

Recovery

TPOS

TNEG

TCLK

RCLK

RPOS

RNEG

Encoder

TTIP

TRING

RTIP

RRING