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| 型号： | XRT83SL30IVTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 52/76页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 SGL 64TQFP |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
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XRT83SL30
53
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
D3
NLCD
Network Loop-Code Detection:
This bit operates differently in the Manual or the Automatic Net-
work Loop-Code detection modes.
In the Manual Loop-Code detection mode (NLCDE1 =”0” and
NLCDE0 =”1”, or NLCDE1 =”1” and NLCDE0 =”0”) this bit gets
set to “1” as soon as the Loop-Up (“00001”) or Loop-Down
(“001”) code is detected in the receive data for longer than 5 sec-
onds. The NLCD bit stays in the “1” state for as long as the chip
detects the presence of the Loop-Code in the receive data and it
is reset to “0” as soon as it stops receiving it. In this mode if the
NLCD interrupt is enabled the chip will initiate an interrupt on
every transition of the NLCD.
When the Automatic Loop-Code detection mode (NLCDE1 =”1”
and NLCDE0 =”1”) is initiated, the state of the NLCD interface bit
is reset to “0” and the chip is programmed to monitor the receive
input data for the Loop-Up Code. This bit is set to a “1” to indicate
that the Network Loop Code is detected for more than 5 sec-
onds. Simultaneously the Remote Loop-Back condition is auto-
matically activated and the chip is programmed to monitor the
receive data for the Network Loop-Down Code. The NLCD bit
stays in the “1” state for as long as the Remote Loop-Back condi-
tion is in effect even if the chip stops receiving the Loop-Up
Code. Remote Loop-Back is removed if the chip detects the
“001” pattern for longer than 5 seconds in the receive data.
Detecting the “001” pattern also results in resetting the NLCD
interface bit and initiating an interrupt provided the NLCD inter-
rupt enable bit it active. When programmed in the Automatic
detection mode, the NLCD interface bit stays “High” for the entire
time the Remote Loop-Back is active and initiates an interrupt
anytime the status of the NLCD bit changes. In this mode the
host can monitor the state of the NLCD bit to determine if the
Remote Loop-Back is activated.
RO
0
D2
AISD
Alarm Indication Signal Detect:
This bit is set to a "1" to indi-
cate All Ones Signal is detected by the receiver. The value of this
bit is based on the current status of Alarm Indication Signal
detector. If the AISDIE bit is enabled, any transition on this bit will
generate an Interrupt.
RO
0
D1
RLOS
Receive Loss of Signal:
This bit is set to a "1" to indicate that
the receive input signal is lost. The value of this bit is based on
the current status of the receive input signal. If the RLOSIE bit is
enabled, any transition on this bit will generate an Interrupt.
RO
0
D0
QRPD
Quasi-random Pattern Detection:
This bit is set to a "1" to indi-
cate the receiver is currently in synchronization with QRSS pat-
tern. The value of this bit is based on the current status of Quasi-
random pattern detector of. If the QRPDIE bit is enabled, any
transition on this bit will generate an Interrupt.
RO
0
TABLE 23: MICROPROCESSOR REGISTER #5 BIT DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83SL314 | 制造商:EXAR 制造商全称:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL314_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL314ES | 功能描述:LIN 收发器 14 CHT1/E1 LIUSH RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
| XRT83SL314IB | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL314IB-F | 功能描述:LIN 收发器 RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8 |
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