- 您现在的位置：买卖IC网 > PDF目录206198 > XRT83SL34 (Exar Corporation) QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PDF资料下载
参数资料
| 型号： | XRT83SL34 |
| 厂商： | Exar Corporation |
| 英文描述： | QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | 上海四的T1/E1/J1收发器时钟恢复和抖动衰减器 |
| 文件页数： | 17/80页 |
| 文件大小： | 856K |
| 代理商： | XRT83SL34 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
21
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram.
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION
FIGURE 8. RECEIVE CLOCK AND OUTPUT DATA TIMING
Norm alized up to +29dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
相关PDF资料 |
PDF描述 |
|---|---|
| XS2F-A422-90-A | 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET |
| XS2F-A422-A90-A | 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET |
| XS2F-A422-AB0-A | 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET |
| XS2F-A422-AC0-A | 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET |
| XS2F-A422-AD0-A | 4 CONTACT(S), POLYBUTYLENE TEREPHTHALATE, FEMALE, CIRCULAR CONNECTOR, CLAMP, SOCKET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83SL34ES | 功能描述:外围驱动器与原件 - PCI 4 CHT1/E1 LIUSH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL34IV | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT83SL34IV-F | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT83SL38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL38_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER |
发布紧急采购，3分钟左右您将得到回复。