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参数资料
| 型号： | XRT83SL34 |
| 厂商： | Exar Corporation |
| 英文描述： | QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | 上海四的T1/E1/J1收发器时钟恢复和抖动衰减器 |
| 文件页数： | 3/80页 |
| 文件大小： | 856K |
| 代理商： | XRT83SL34 |
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XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.8
8
MICROPROCESSOR INTERFACE
SIGNAL NAME
PIN #TYPE
DESCRIPTION
HW_HOST
68
I
Mode Control Input
This pin selects Hardware or Host mode. Leave this pin unconnected or tie
“High” to select Hardware mode.
For Host mode, this pin must be tied “Low”.
NOTE: Internally pulled “High” with a 50k
resistor.
WR_R/W
TAOS_0
69
I
Write Input (Read/Write) - Host mode
Intel bus timing: A “Low” pulse on WR selects a write operation when CS
pin is “Low”.
Motorola bus timing: A “High” pulse on R/W selects a read operation and a
“Low” pulse on R/W selects a write operation when CS is “Low”.
Transmit All “Ones” Channel_0 - Hardware Mode
NOTE: Internally pulled “Low” with a 50k
resistor.
RD_DS
TAOS_1
70
I
Read Input (Data Strobe) - Host Mode
Intel bus timing: A “Low” pulse on RD selects a read operation when the CS
pin is “Low”.
Motorola bus timing: A “Low” pulse on DS indicates a read or write opera-
tion when the CS pin is “Low”.
Transmit All “Ones” Channel_1 - Hardware Mode
NOTE: Internally pulled “Low” with a 50k
resistor.
ALE_AS
TAOS_2
71
I
Address Latch Input (Address Strobe) - Host Mode
Intel bus timing: The address inputs are latched into the internal register on
the falling edge of ALE.
Motorola bus timing: The address inputs are latched into the internal regis-
ter on the falling edge of AS.
Transmit All “Ones” Channel_2 - Hardware Mode
NOTE: Internally pulled “Low” with a 50k
resistor.
CS
TAOS_3
72
I
Chip Select Input - Host Mode
This signal must be “Low” in order to access the parallel port.
Transmit All “Ones” Channel_3 - Hardware Mode
NOTE: Internally pulled “Low” with a 50k
resistor.
RDY_DTACK
RXMUTE
73
O
I
Ready Output (Data Transfer Acknowledge Output) - Host Mode
Intel bus timing: RDY is asserted “High” to indicate the device has com-
pleted a read or write operation.
Motorola bus timing: DTACK is asserted "Low" to indicate the device has
completed a read or write cycle.
Receive Muting - Hardware mode
NOTE: Internally pulled “Low” with a 50k
resistor.
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相关代理商/技术参数 |
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| XRT83SL38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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