参数资料
| 型号： | XRT91L33IG-F |
| 厂商： | Exar Corporation |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC MULTIRATE CDR 20TSSOP |
| 标准包装： | 10 |
| 类型： | 时钟和数据恢复（CDR），时钟/频率同步器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | LVDS，LVPECL |
| 输出： | LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 散装 |
| 其它名称： | 1016-1362 |
XRT91L33
4
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
1.0
PIN DESCRIPTIONS
TABLE 2: PIN DESCRIPTION TABLE
NAME
LEVEL
TYPE
PIN
DESCRIPTION
VDDA
PWR
1
3.3V Power supply
RXDIP
LVDS/PECL
I
2
Positive side of receive data input. The high-speed output clock
(RXCLKOP/N) is recovered from this high-speed differential
inupt data.
RXDIN
LVDS/PECL
I
3
Negative side of receive data input. The high-speed output
clock (RXCLKOP/N) is recovered from this high-speed differen-
tial input data.
VSSA
PWR
4
Ground pin
LOCK
LVPECL
O
5
Active HIGH to indicate that the PLL is locked to serial data
input and valid clock and data are present at the serial outputs
(RXDOP/N and RXCLKOP/N). The LOCK will go inactive under
the following conditions:
If SIGD is set LOW
If LCKTOREFN is set LOW
If the VCO has drifted away from the local reference
clock, REFCK, by more than +/- 500 ppm
STS12_MODE
LVTTL
I
6
STS-12 or STS-3 mode selection.
Set HIGH to select the
STS-12 operation. Set LOW for STS-3 operation
REFCK
LVTTL
I
7
Local 19.44 MHz reference clock input for the CDR. REFCK is
used for the PLL phase adjustment during power up. It also
serves as a stable clock source in the absence of serial input
data.
LCKTOREFN
LVTTL
I
8
Lock to REFCK input. When set LOW, this pin causes the out-
put clock, RXCLKOP/N to be held within +/- 500ppm of the
input reference clock REFCL and forces the RXDOP/N to a low
state.
VSS
PWR
9
Ground pin
VDD
PWR
10
3.3V power supply
RXCLKON
LVDS/
LVPECL
O
11
High-speed clock output, negative.
This clock is recovered
from the receive data input (RXDIP/N) and supports either
LVDS or LVPECL termination
RXCLKOP
LVDS/
LVPECL
O
12
High-speed clock output, positive This clock is recovered from
the receive data input (RXDIP/N) and supports either LVDS or
LVPECL. termination
RXDON
LVDS/
LVPECL
O
13
High-speed output, negative This is the retimed version of the
recovered data stream from RXDIP/N and can be in either LVDS
or LVPECL termination
RXDOP
LVDS/
LVPECL
O
14
High-speed output, positive. This is the retimed version of the
recovered data stream from RXDIP/N and can be in either
LVDS or LVPECL termination
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L33IGTR-F | 功能描述:时钟发生器及支持产品 Recovery Unit RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| XRT91L34 | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR |
| XRT91L34ES | 功能描述:外围驱动器与原件 - PCI 4 CHOC12/STM4 OC3/STM1 CDR RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT91L34IV | 功能描述:计时器和支持产品 4CH OC12/STM4 OC3/STM1CDR RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| XRT91L34IVF | 制造商:Exar Corporation 功能描述:CDR 51.84Mbps/155.52Mbps/622.08Mbps SONET/SDH 128-Pin LQFP 制造商:EXAR 功能描述:CDR 51.84Mbps/155.52Mbps/622.08Mbps SONET/SDH 128-Pin LQFP |
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