参数资料
| 型号： | XRT91L33IG-F |
| 厂商： | Exar Corporation |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC MULTIRATE CDR 20TSSOP |
| 标准包装： | 10 |
| 类型： | 时钟和数据恢复（CDR），时钟/频率同步器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | LVDS，LVPECL |
| 输出： | LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 622.08MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 散装 |
| 其它名称： | 1016-1362 |
XRT91L33
7
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION
2.6
Lock Detection
XRT91L33 features a PLL lock detection circuit. The lock detect (LOCK) output goes HIGH to indicate that the
PLL is locked to the serial data input and valid data and clock are present at the high-speed differential output.
The LOCK output will go LOW if either the LOCKTOREFN or the SIGD input is forced LOW. Additionally,
LOCK will also go low if the incoming data frequency is more than +/-500ppm away from the reference clock
frequency (REFCK x 32 in OC12 mode, REFCLK x 8 in OC3 mode). When LOCK output is driven LOW, the
VCO is forced to lock to REFCK and then released to lock on the incoming data. If the incoming data frequency
remains outside the +/-500ppm window, the training mode is repeated. Debounce logic stabilizes the LOCK
output pin to stay LOW for incoming frequencies well beyond the +/-500ppm window.
2.7
PLL Test Operation
The TEST pin is intended for use in production test and should be set at logic LOW in normal operation. If both
TEST and STS12_MODE pins are set to logic HIGH, XRT91L33 will bypass the PLL and present an inverted
version of the REFCK to the clock output RXCLKOP/N. REFCK’s rising edge is used to capture the input data
and transmit data to RXDOP/N. This bypass test operation can be used to facilitate board level debugging
process.
0
1
LOS (Internal)
SIGD
LCKTOREFN
TEST
STS12_MODE
REFCK
PLL Clock
(Internal)
RXDIP/N
22
2
RXCLKOP/N
RXDOP/N
相关PDF资料 |
PDF描述 |
|---|---|
| XRT91L34IV-F | IC MULTIRATE CDR QUAD 128LQFP |
| 07010 | CALIBRATION UNIT NIST STD WS&FG |
| 07200 | CHAIR COVER STATSHIELD |
| 07420 | BINDER 3RING DISSIPATIVE 3" |
| 07450 | SHEET PROT'R CLR 8.75X11.25 25PK |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L33IGTR-F | 功能描述:时钟发生器及支持产品 Recovery Unit RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| XRT91L34 | 制造商:EXAR 制造商全称:EXAR 功能描述:QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR |
| XRT91L34ES | 功能描述:外围驱动器与原件 - PCI 4 CHOC12/STM4 OC3/STM1 CDR RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT91L34IV | 功能描述:计时器和支持产品 4CH OC12/STM4 OC3/STM1CDR RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| XRT91L34IVF | 制造商:Exar Corporation 功能描述:CDR 51.84Mbps/155.52Mbps/622.08Mbps SONET/SDH 128-Pin LQFP 制造商:EXAR 功能描述:CDR 51.84Mbps/155.52Mbps/622.08Mbps SONET/SDH 128-Pin LQFP |
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