参数资料
型号: XRT91L34IV
厂商: Exar Corporation
文件页数: 17/38页
文件大小: 0K
描述: IC MULTIRATE CDR QUAD 128LQFP
标准包装: 72
类型: 时钟和数据恢复(CDR),扇出缓冲器(分配),多路复用器
PLL:
主要目的: SONET/SDH,STS,STM
输入: LVDS,LVPECL
输出: LVDS,LVPECL
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 1.71 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x14)
包装: 托盘
XRT91L34
24
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
4.0
SERIAL MICROPROCESSOR INTERFACE BLOCK
The Serial Microprocessor Interface uses a standard 3-pin serial port with CS, SCLK, and SDI for programming
the device. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers,
monitor the device via an interrupt pin, and reset the device to its default configuration by pulling reset "Low"
for more than 10ns. A simplified block diagram of the Serial Microprocessor Interface is shown in Figure 17.
4.1
SERIAL TIMING INFORMATION
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
Interface samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device
until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor Interface is
shown in Figure 18.
NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active
"Low") must be de-asserted at the end of each write or read operation.
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE
FIGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE
Shift Register
Data out
Register
Bank
Address
bus
Data
bus
Status bits and error
Flags from CDRs
Controls to
CDRs
RESET
CS
INT
SDI
SCLK
SDO
CS
SDI
SCLK
SDO
1
2
10
9
8
7
6
5
4
3
11
16
15
13
14
12
R/W
A0
A1
A2
A3
A4
A5
X
D0
D1
D7
D6
D5
D4
D3
D2
D0
D1
D7
D6
D5
D4
D3
D2
High-Z
25nS
50nS
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