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| 型号： | ZL50408GDC |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208 |
| 文件页数： | 65/144页 |
| 文件大小： | 1779K |
| 代理商： | ZL50408GDC |
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ZL50408
Data Sheet
27
Zarlink Semiconductor Inc.
2.1
Internal Memory
Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB), storing of MAC Control Table
database (MCT), and the Network Management (NM) Database statistics counters and MIB.
The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the
received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the
egress port.
A memory arbiter is used to arbitrary the memory access requests from various sources. A Built In Self Test (BIST)
is used to detect any error in the memory array when the device is powered up. The BIST can also be requested by
the writing to the GCR register.
2.2
MAC Modules
2.2.1
RMII MAC Module (RMAC)
The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). It has five interfaces: MII, RMII, GPSI (only for 10M),
Reverse MII, or Reverse GPSI (only for 10M).
The RMAC of the ZL50408 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full
Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon
collision for up to 16 total transmissions.
These eight ports are denoted as ports 0 to 7. The PHY addresses for the PHY devices connected to the 8 RMAC
ports has to be from 08h (port 0) to 0Fh (port 7).
2.2.1.1
GPSI (7WS) Interface
The RMAC ethernet port can function in GPSI (7WS) mode. In this mode, the TXD[0], RXD[0] serve as TX data, RX
data and respectively. The link and duplex of the port can be controlled by programming the ECR1Pn register. Only
port-based VLAN is supported with GPSI interface.
2.2.2
CPU MAC Module (CMAC)
The CPU Media Access Control (CMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external CPU device. It support either a Reverse MII interface, providing the necessary
interface TX and RX clocks to the CPU, or a register access mechanism via the 8/16-bit or serial interface.
Using the MII interface, the CMAC of the ZL50408 device meets the IEEE 802.3 specification. It is able to operate
in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically
retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 8.
2.2.3
GMII MAC Module (GMAC)
The GMII Media Access Control (GMAC) module provides the necessary buffers and control interface between the
Frame Engine (FE) and the external physical device (PHY). The GMAC implements both GMII and MII interface,
which offers a simple migration from 10/100 to 1G.
The GMAC of the ZL50408 device meets the IEEE 802.3Z specification. It is able to operate in 10 M/100 M either
Half or Full Duplex mode with a back pressure/flow control mechanism or in 1G Full duplex mode with flow control
mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions.
This port is denoted as port 9. The PHY address for the PHY device connected to the GMAC port has to be 10h.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50408GDG2 | 制造商:Microsemi Corporation 功能描述: |
| ZL50409 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL50410 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
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