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参数资料
| 型号： | ZL50408GDC |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 网络接口 |
| 英文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, MO-192, LBGA-208 |
| 文件页数： | 73/144页 |
| 文件大小： | 1779K |
| 代理商： | ZL50408GDC |
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ZL50408
Data Sheet
34
Zarlink Semiconductor Inc.
To indirectly configure the register addressed by the index register(s), a “data” register (address 010b) must
be written with the desired 8-bit data.
The ZL50408 supports special register-write in serial and 16-bit mode. This allows CPU to write to two
consecutive configuration registers in a single write operation. By writing to bit[14] of configuration
register address, CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address
specified in index register and upper 8 bit of data is for the address + 1. In 8-bit mode, this special feature
will be ignored.
Similarly, to read the value in the register addressed by the index register(s), the “data” register can now
simply be read.
The ZL50408 supports an incremental read/write. If CPU requires to read or write to the configuration
registers incrementally, CPU only has to write to index register once with the MSB of configuration register
address set and then CPU can continuously reading or writing to “data” register (010b).
In summary, access to the many internal registers is carried out simply by directly accessing only two registers –
one register to indicate the index of the desired parameter, and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
3.1.2
Rx/Tx of Standard Ethernet Frames
In serial mode with MII, the MII interface is used for CPU to transmit and receive Ethernet frames. In 8/16-bit or
serial only mode, the Ethernet frame is transmitted and received through the CPU interface. There is no ability to
send/receive Ethernet frames in unmanaged mode.
To transmit a frame from the CPU in 8/16-bit or serial only mode:
The CPU writes to the “data frame” register (address 011) with the frame size, destination port number, and
frame status. After writing all the transmitting status bytes, it then writes the data it wants to transmit
(minimum 64 bytes).
The ZL50408 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
To receive a frame into the CPU in 8/16-bit or serial only mode:
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size, and
VLAN tag.
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
To transmit a frame from the CPU with MII interface:
ZL50408 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive
clock to send packets to ZL50408
ZL50408 has the ability to halt the receive clock if the receive FIFO of ZL50408 is overflow. Transmitting from
CPU to ZL50408 will resume once the receive FIFO of ZL50408 is no longer overflow
Follow the standard Ethernet transmission format. CPU assert receive data valid (RXDV) before transmitting
data to ZL50408 and de-assert RXDV after transmitting the last data
To receive a frame into the CPU with MII interface:
ZL50408 acts as a PHY to provide transmit clock (TXCLK) to CPU so the CPU will depend on the transmit
clock to receive packets from ZL50408
ZL50408 has the ability to halt the transmit clock if the transmit FIFO of ZL50408 is under-run. CPU will
resume receiving packets from ZL50408 once the transmit FIFO of ZL50408 is no longer under-run
15
14
13
12
0
11
12 Bit Register Address
Reserved
INC
R/W
SP
W
相关PDF资料 |
PDF描述 |
|---|---|
| ZL50408GDG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA208 |
| ZL50418GKG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| ZL50418/GKC | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| ZL50418GKG2 | DATACOM, LAN SWITCHING CIRCUIT, PBGA553 |
| ZLW-2-B | 1 MHz - 1000 MHz RF/MICROWAVE DOUBLE BALANCED MIXER, 9.5 dB CONVERSION LOSS-MAX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL50408GDG2 | 制造商:Microsemi Corporation 功能描述: |
| ZL50409 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 9-Port 10/100M Ethernet Switch |
| ZL50409GDC1 | 制造商:Microsemi Corporation 功能描述: |
| ZL50410 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Managed 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch |
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