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参数资料
| 型号： | ZY7007LG-T3 |
| 厂商： | Power-One |
| 文件页数： | 20/35页 |
| 文件大小： | 0K |
| 描述： | PROGBL CONVERT DC-DC 7A OUT SMD |
| 特色产品： | ZY Series Converters |
| 标准包装： | 1 |
| 系列： | 智能 POL 转换器 |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 3V |
| 电压 - 输入（最大）： | 14V |
| Voltage - Output 1： | 0.5 ~ 5.5 V |
| 电流 - 输出（最大）： | 7A |
| 电源（瓦） - 制造商系列： | 38W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-DIP SMD 模块 |
| 尺寸/尺寸： | 0.87" L x 0.49" W x 0.26" H（22.2mm x 12.5mm x 6.5mm） |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 电源（瓦特）- 最大： | 38.5W |
| 产品目录页面： | 2739 (CN2011-ZH PDF) |
| 其它名称： | 179-2410-6 |
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ZY7007 7A DC-DC Intelligent POL Data Sheet
3V to 14V Input ? 0.5V to 5.5V Output
If the falling slew rate control is not utilized, the turn-
off delay only determines an interval from the
application of the Turn-Off command until both high
side and low side switches are turned off. In this
U
---
Bit 7
R/W-0
R2
R/W-0
R1
R/W-0
R0
R/W-1
SC
R/W-0
F2
R/W-0
F1
R/W-0
F0
Bit 0
case, the output voltage ramp-down process is
determined by load parameters.
8.2.3 Rising and Falling Slew Rates
The output voltage tracking is accomplished by
programming the rising and falling slew rates of the
output voltage. To achieve programmed slew rates,
the output voltage is being changed in 12.5mV steps
where duration of each step determines the slew
rate. For example, ramping up a 1.0V output with a
slew rate of 0.5V/ms will require 80 steps duration of
25 μ s each.
Bit 7 Unimplemented , read as ‘0’
Bit 6:4 R[2:0] : Value of Vo rising slope
0: corresponds to 0.1V/ms (default)
1: corresponds to 0.2V/ms
2: corresponds to 0.5V/ms
3: corresponds to 1.0V/ms
4: corresponds to 2.0V/ms
5: corresponds to 5.0V/ms
6: corresponds to 8.3V/ms
7: corresponds to 8.3V/ms
Bit 3 SC , Slew rate control at turn-off
0: Slew rate control is disabled
1: Slew rate control is enabled
Bit 2:0 F[2:0] : Value of Vo falling slope
0: corresponds to -0.1V/ms (default)
1: corresponds to -0.2V/ms
2: corresponds to -0.5V/ms
3: corresponds to -1.0V/ms
4: corresponds to -2.0V/ms
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Duration of each voltage step is calculated by
dividing the master clock frequency generated by the
DPM. Since all POLs in the system are
synchronized to the master clock, the matching of
5: corresponds to -5.0V/ms
6: corresponds to –8.3V/ms
7: corresponds to –8.3V/ms
Figure 34. Tracking Configuration Register TC
voltage slew rates of different outputs is very
accurate as it can be seen in Figure 8 and Figure 12.
8.3
Protections
During the turn on process, a POL not only delivers
current required by the load (I LOAD ), but also charges
the load capacitance. The charging current can be
determined from the equation below:
ZY7007 Series converters have a comprehensive set
of programmable protections. The set includes the
output over- and undervoltage protections,
overcurrent protection, overtemperature protection,
tracking protection, overtemperature warning, and
Power Good signal. Status of protections is stored in
I CHG ? C LOAD ? dV R
dt
the ST register shown in Figure 35.
Where, C LOAD is load capacitance, dV R /dt is rising
voltage slew rate, and I CHG is charging current.
R-1
TP
Bit 7
R-0
PG
R-1
TR
R-1
OT
R-1
OC
R-1
UV
R-1
OV
R-1
PV
Bit 0
When selecting the rising slew rate, a user needs to
ensure that
I LOAD ? I CHG ? I OCP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TP : Temperature Warning
PG : Power Good Warning
TR : Tracking Fault
OT : Overtemperature Fault
OC : Overcurrent Fault
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Where I OCP is the overcurrent protection threshold of
the ZY7007. If the condition is not met, then the
overcurrent protection will be triggered during the
turn-on process. To avoid this, dV R /dt and the
overcurrent protection threshold should be
programmed to meet the condition above.
Bit 2 UV : Undervoltage Fault
Bit 1 OV : Overvoltage Error
Bit 0 PV : Phase Voltage Error
Note:
- An activated warning/fault/error is encoded as ‘0’
Figure 35. Protection Status Register ST
Thresholds of overcurrent, over- and undervoltage
protections, and Power Good limits can be
programmed in the GUI Output Configuration
window or directly via the I 2 C bus by writing into the
CLS and PC2 registers shown in Figure 36 and
Figure 37.
ZD-00245 Rev. 2.6, 01-Jul-10
www.power-one.com
Page 20 of 35
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZY7007L-T3 | 制造商:Power-One 功能描述:- Tape and Reel |
| ZY7007LU-Q1 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output |
| ZY7007LU-T1 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output |
| ZY7007LU-T2 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output |
| ZY7007LU-T3 | 制造商:POWER-ONE 制造商全称:Power-One 功能描述:7A DC-DC Intelligent POL 3V to 14V Input - 0.5V to 5.5V Output |
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