参数资料
| 型号： | 24C02CT-I/MNY |
| 厂商： | Microchip Technology |
| 文件页数： | 6/30页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ 8TDFN |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN（2x3） |
| 包装： | 标准包装 |
| 产品目录页面： | 1445 (CN2011-ZH PDF) |
| 其它名称： | 24C02CT-I/MNYDKR |
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24C02C
3.0
FUNCTIONAL DESCRIPTIONS
4.4
Data Valid (D)
The 24C02C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access, and generates the Start
and Stop conditions, while the 24C02C works as slave.
Both master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
4.0
BUS CHARACTERISTICS
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
overwrite does occur it will replace data in a first-in first-
out fashion.
is not busy.
? During data transfer, the data line must remain
4.5
Acknowledge
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
defined (Figure 4-1).
Note:
The 24C02C does not generate any
Acknowledge bits if an internal
4.1
Bus Not Busy (A)
programming cycle is in progress.
Both data and clock lines remain high.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
4.2
Start Data Transfer (B)
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
4.3
Stop Data Transfer (C)
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 4-2).
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.
DS21202J-page 6
? 2008 Microchip Technology Inc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24C02CTISN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24C02CTIST | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24C02CTSN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24C02CTST | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24C02CW | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
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