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参数资料
| 型号： | 24LCS61/ST |
| 元件分类： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | TSSOP-8 |
| 文件页数： | 12/17页 |
| 文件大小： | 249K |
| 代理商： | 24LCS61/ST |
24LCS61/62
DS21226C-page 4
Preliminary
1999 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
SDA (Serial Data)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 k
for 100 kHz, 2 k for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions. The SDA pin has Schmitt trigger and filter circuits
which suppress noise spikes to assure proper device
operation even on a noisy bus
2.2
SCL (Serial Clock)
This input is used to synchronize the data transfer from
and to the device. The SCL pin has Schmitt trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
2.3
EDS (External Device Select)
The External Device Select (EDS) pin is an open drain
output that is controlled by using the OE bit in the con-
trol byte. It can be used to enable other circuitry when
the device is selected. A pull-up resistor must be added
to this pin for proper operation. This pin should not be
pulled up to a voltage higher than Vcc+1V. See
Section 9.0 for more details.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between the START and STOP
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(A)
(C)
SCL
SDA
START
CONDITION
DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LCS61T/SN | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS61T/ST | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS61T-I/SN | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS61T-I/ST | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS62/P | 功能描述:电可擦除可编程只读存储器 256x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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