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参数资料
| 型号： | 24LCS61/ST |
| 元件分类： | PROM |
| 英文描述： | 128 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | TSSOP-8 |
| 文件页数： | 6/17页 |
| 文件大小： | 249K |
| 代理商： | 24LCS61/ST |
24LCS61/62
DS21226C-page 14
Preliminary
1999 Microchip Technology Inc.
9.0
EXTERNAL DEVICE SELECT
(EDS) PIN AND OUTPUT
ENABLE (OE) BIT
The External Device Select (EDS) pin is an open drain,
low active output and may be used by the system
designer for functions such as enabling other circuitry
when the 24LCS61/62 is being accessed. Because the
pin is an open drain output, a pull-up resistor is required
for proper operation of this pin. When the device is pow-
ered up, the EDS pin will always be in the high imped-
ance state (off). The EDS pin function is controlled by
using the output enable (OE) bit in the control byte of
each command. If the OE bit is high, the EDS pin is
enabled and if the OE bit is low the pin is disabled. For
the Assign Address command and standard read or
write commands, the EDS pin will pull low (providing
that the OE bit is set high) on the rising clock edge after
the ack bit following the ID byte. See Figure 9-1. For
commands such as the Clear Address command, the
EDS pin will change states at the rising clock edge just
before the Stop bit. It is also possible to control the EDS
pin by sending a partial command such as the control
byte and ID byte for a write command followed by the
Stop bit. The EDS pin would change states just before
the Stop bit as shown in the lower portion of Figure 9-
1. When the EDS pin has changed states, it is latched
and will remain in a given state until another command
is sent to the device with the OE bit set to change the
state of the pin, or power to the device is removed.
FIGURE 9-1:
EDS PIN OPERATION
SCL
9
8
7
6
5
4
3
2
1
123
For commands such as the Assign Address command or standard read and
writes, the EDS pin will be asserted on this rising clock edge if the OE bit was set
to a one in the control byte. If the OE bit is a zero and the previous command
asserted it, then the EDS pin will be released by the device on this clock edge.
SDA
9
8
7
6
51
2
3
0
1
0
Start
Bit
Control
Byte
ACK
BIT
4
ID Byte
ACK
BIT
SCL
9
8
7
6
5
4
3
2
1
123
For commands such as the Clear Address command, the command is ter-
minated at this point with a STOP bit. The EDS pin will be asserted on this
rising clock edge if the OE bit was set to a one in the control byte. If the OE
bit is a zero and the previous command asserted it, then the EDS pin will be
released by the device at this point.
SDA
9
8
7
6
5
0
1
0
Start
Bit
Control
Byte
ACK
BIT
4
ID Byte
ACK
BIT
STOP
BIT
EDS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LCS61T/SN | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS61T/ST | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS61T-I/SN | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS61T-I/ST | 功能描述:电可擦除可编程只读存储器 128x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| 24LCS62/P | 功能描述:电可擦除可编程只读存储器 256x8 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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