参数资料
| 型号： | 3336-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 11/13页 |
| 文件大小： | 0K |
| 描述： | IC PLL INTEGER-N 3GHZ 48-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 类型： | 预分频器，整数 N |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.85 V ~ 3.15 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 标准包装 |
| 其它名称： | 1046-1014-6 |
Product Specification
PE3336
Document No. 70-0033-05
│ www.psemi.com
Page 7 of 13
2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Functional Description
The PE3336 consists of a prescaler, counters, a
phase detector and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired direct to the pins. There
are also various operational and test modes and
lock detect.
Figure 3. Functional Block Diagram
Control
Logic
R Counter
(6-bit)
Phase
Detector
fc
PD_U
PD_D
R(5:0)
M(8:0)
A(3:0)
D(7:0)
Sdata
Control
Pins
fr
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
2k
Cext
fp
Fin
Obsolete
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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