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参数资料
| 型号： | 37C669 |
| 厂商： | SMSC Corporation |
| 英文描述： | DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL |
| 中文描述： | 电脑98/99顺从超级I / O软盘控制器与红外线支持 |
| 文件页数： | 144/164页 |
| 文件大小： | 621K |
| 代理商： | 37C669 |
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80
Bit 0
Delta Clear To Send (DCTS).
Bit 0 indicates
that the nCTS input to the chip has changed
state since the last time the MSR was read.
Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates
that the nDSR input has changed state since
the last time the MSR was read.
Bit 2
Trailing Edge of Ring Indicator (TERI).
Bit 2
indicates that the nRI input has changed from
logic "0" to logic "1".
Bit 3
Delta Data Carrier Detect (DDCD).
Bit 3
indicates that the nDCD input to the chip has
changed state.
NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic
"1", a MODEM Status Interrupt is generated.
Bit 4
This bit is the complement of the Clear To Send
(nCTS) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set
Ready (nDSR) input. If bit 4 of the MCR is set
to logic "1", this bit is equivalent to DTR in the
MCR.
Bit 6
This bit is the complement of the Ring Indicator
(nRI) input. If bit 4 of the MCR is set to logic
"1", this bit is equivalent to OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier
Detect (nDCD) input. If bit 4 of the MCR is set
to logic "1", this bit is equivalent to OUT2 in the
MCR.
SCRATCHPAD REGISTER (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the
operation of the Serial Port. It is intended as a
scratchpad
register
to
be
used
by
the
programmer to hold data temporarily.
PROGRAMMABLE BAUD RATE GENERATOR
(AND DIVISOR LATCHES DLH, DLL)
The Serial Port contains a programmable Baud
Rate Generator that is capable of taking any
clock input (DC to 3 MHz) and dividing it by any
divisor from 1 to 65535. This output frequency
of the Baud Rate Generator is 16x the Baud
rate. Two 8 bit latches store the divisor in 16 bit
binary format. These Divisor Latches must be
loaded during initialization in order to insure
desired operation of the Baud Rate Generator.
Upon loading either of the Divisor Latches, a 16
bit Baud counter is immediately loaded.
This
prevents long counts on initial load.
If a 0 is
loaded into the BRG registers the output divides
the clock by the number 3. If a 1 is loaded the
output is the inverse of the input oscillator. If a
two is loaded the output is a divide by 2 signal
with a 50% duty cycle.
If a 3 or greater is
loaded the output is low for 2 bits and high for
the remainder of the count. The input clock to
the BRG is the 24 MHz crystal divided by 13,
giving a 1.8462 MHz clock.
Table 33 shows the baud rates possible with a
1.8462 MHz crystal.
Effect Of The Reset on Register File
The Reset Function Table (Table 34) details the
effect of the Reset input on each of the registers
of the Serial Port.
相关PDF资料 |
PDF描述 |
|---|---|
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| 37C67X | ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
| 37C957FR | ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS |
| 37FMA1-ABW31N | SPECIAL SWITCH-PIEZO SWITCH, SPST, MOMENTARY, 0.2A, 24VDC, PANEL MOUNT-THREADED |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 37C672 | 制造商:SMSC 制造商全称:SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
| 37C67X | 制造商:SMSC 制造商全称:SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
| 37C-6BH-5-5 | 制造商:Birtcher Products 功能描述: |
| 37C72U-185 | 制造商:White-Rodgers 功能描述: |
| 37C73U-170 | 制造商:White-Rodgers 功能描述: |
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