参数资料
型号: 37C669
厂商: SMSC Corporation
英文描述: DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL
中文描述: 电脑98/99顺从超级I / O软盘控制器与红外线支持
文件页数: 27/164页
文件大小: 621K
代理商: 37C669
122
CR01
This register can only be accessed in the
Configuration
Mode
and after the CSR has
been initialized to 01H. The default value of this
register after power up is 9CH.
Table 48 - CR01
BIT NO.
BIT NAME
DESCRIPTION
0,1
Reserved
Read Only. A read returns a 0.
2
Parallel Port
Power (see note
_PWRDN)
A high level on this bit, supplies power to the Parallel Port
(Default).
A low level on this bit puts the Parallel Port in low
power mode.
3
Parallel Port
Mode
Parallel Port Mode. A high level on this bit, sets the Parallel Port
for Printer Mode (Default). A low level on this bit enables the
Extended Parallel port modes. Refer to Bits 0 and 1 of CR4
4
Reserved
Read Only. A read returns a 1.
5,6
Reserved
Read Only. A read returns a 0.
7
Lock CRx
A high level on this bit enables the reading and writing of CR00-
CR18 (Default). A low level on this bit disables the reading and
writing of CR0-CRF. Once set to 0, this bit can only be set to 1
by a hard reset or power-up reset.
CR02
This
register
can
only be accessed in the
Configuration Mode and after the CSR has been
initialized to 02H.
The default value of this
register after power up is 88H.
Table 49 - CR02
BIT NO.
BIT NAME
DESCRIPTION
0:2
Reserved
Read Only. A read returns a 0.
3
UART1 Power
down (see note
_PWRDN)
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
4:6
Reserved
Read Only. A read returns a 0.
7
UART2 Power
down
A high level on this bit, allows normal operation of the Secondary
Serial Port (Default). A low level on this bit places the Secondary
Serial Port into Power Down Mode.
Note_PWRDN:
Power Down bits disable the respective logical device and associated pins, however
the power down bit does not disable the selected address range registers for the
logical device.
To disable the host address registers the logical device's base
address must be set below 100h. Therefore devices which are powered down, but
still reside at a valid I/O base address will participate in Plug-and-Play range
checking.
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