
96
EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of
which are listed below. The individual features
are explained in greater detail in the remainder
of this section.
High performance half-duplex forward and
reverse channel
Interlocked handshake, for fast reliable
transfer
Optional single byte RLE compression for
improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
Vocabulary
The following terms are used in this document:
assert
When
a
signal
asserts
it
transitions to a "true" state, when a
signal deasserts it transitions to a
"false" state.
forward Host to Peripheral communication.
reverse Peripheral to Host communication.
PWord A port word; equal in size to the
width of the ISA interface.
For this
implementation, PWord is always 8
bits.
1
A high level.
0
A low level.
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document:
IEEE 1284 Extended Capabilities Port Protocol
and ISA Interface Standard, Rev 1.09, Jan 7,
1993.
This
document
is
available
from
Microsoft.
The bit map of the Extended Parallel Port
registers is:
D7
D6
D5
D4
D3
D2
D1
D0
Note
data
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ecpAFifo
Addr/RL
E
Address or RLE field
2
dsr
nBusy
nAck
PError
Select
nFault
0
1
dcr
0
Direction
ackIntEn
SelectIn
nInit
autofd strobe
1
cFifo
Parallel Port Data FIFO
2
ecpDFifo
ECP Data FIFO
2
tFifo
Test FIFO
2
cnfgA
0
1
0
cnfgB
compress
intrValue
0
ecr
MODE
nErrIntrEn
dmaEn
serviceIntr
full
empty
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.