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参数资料
| 型号： | 4460-TCE10D434-EK |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 17/56页 |
| 文件大小： | 0K |
| 描述： | KIT EZRADIO TEST CARD SI4460 TX |
| 设计资源： | 4460-TCE10D434 BOM 4460-TCE10D434 PCB 4460-TCE10D434 SCH |
| 标准包装： | 1 |
| 系列： | EZRadioPRO® |
| 类型： | 收发器，ISM |
| 频率： | 434MHz |
| 适用于相关产品： | Si4460 |
| 已供物品： | 板 |
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Si4464/63/61/60
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The Si446x communicates with the host MCU over a standard 4-wire serial peripheral interface (SPI): SCLK, SDI,
SDO, and nSEL. The SPI interface is designed to operate at a maximum of 10 MHz. The SPI timing parameters
are demonstrated in Table 8. The host MCU writes data over the SDI pin and can read data from the device on the
SDO output pin. Figure 3 demonstrates an SPI write command. The nSEL pin should go low to initiate the SPI
command. The first byte of SDI data will be one of the firmware commands followed by n bytes of parameter data
which will be variable depending on the specific command. The rising edges of SCLK should be aligned with the
center of the SDI data.
Table 8. Serial Interface Timing Parameters
Symbol
t CH
t CL
Parameter
Clock high time
Clock low time
Min (ns)
40
40
Diagram
t DS
Data setup time
20
SCLK
t SS
t CL
t CH
t DS
t DH
t DD
t SH t DE
t DH
Data hold time
20
t DD
t EN
t DE
Output data delay time
Output enable time
Output disable time
20
20
50
SDI
SDO
t SS
t SH
t SW
Select setup time
Select hold time
Select high period
20
50
80
nSEL
t EN
t SW
nSEL
SDO
SDI
FW Command
Param Byte 0
Param Byte n
SCLK
Figure 3. SPI Write Command
The Si446x contains an internal MCU which controls all the internal functions of the radio. For SPI read commands
a typical MCU flow of checking clear-to-send (CTS) is used to make sure the internal MCU has executed the
command and prepared the data to be output over the SDO pin. Figure 4 demonstrates the general flow of an SPI
read command. Once the CTS value reads FFh then the read data is ready to be clocked out to the host MCU. The
typical time for a valid FFh CTS reading is 20 μs. Figure 5 demonstrates the remaining read cycle after CTS is set
to FFh. The internal MCU will clock out the SDO data on the negative edge so the host MCU should process the
SDO data on the rising edge of SCLK.
Rev 1.2
17
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