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参数资料
| 型号： | 48e30 |
| 厂商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（带EEPROM） |
| 文件页数： | 4/44页 |
| 文件大小： | 351K |
| 代理商： | 48E30 |
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HT48E30
Rev. 0.00
12
January 12, 2004
Preliminary
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, a regular interrupt re-
sponse takes place. If an interrupt request flag is set to
1 before entering the HALT mode, the wake-up func-
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system clock pe-
riod) to resume to normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The time-out during HALT is different from other chip re-
set conditions, since it can perform a
warm reset that
resets only the PC and SP, leaving the other circuits in
their original state. Some registers remain unchanged
during other reset conditions. Most registers are reset to
the
initial condition when the reset conditions are met.
By examining the PDF and TO flags, the program can
distinguish between different
chip resets.
TO PDF
RESET Conditions
0
RES reset during power-up
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
WDT wake-up HALT
Note:
u stands for unchanged”
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able an SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer, SP
Points to the top of the stack
R E S
V D D
1 0 0 k W
1 0 k W
0 . 1 m F *
0 . 0 1 m F *
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
t S S T
R E S
V D D
S S T T i m e - o u t
C h i p R e s e t
Reset Timing Chart
W a r m R e s e t
W D T
H A L T
C o l d
R e s e t
R E S
S y s t e m R e s e t
S S T
1 0 - b i t R i p p l e
C o u n t e r
O S C 1
Reset Configuration
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