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参数资料
| 型号： | 48e30 |
| 厂商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（带EEPROM） |
| 文件页数： | 43/44页 |
| 文件大小： | 351K |
| 代理商： | 48E30 |
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HT48E30
Rev. 0.00
8
January 12, 2004
Preliminary
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
Stack Register
- STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a
CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 4 return ad-
dresses are stored).
Data Memory
- RAM
The data memory has a capacity of 115
8 bits and is di-
vided into two functional groups: special function regis-
ters and general purpose data memory (96
8). Most
are read/write, but some are read only.
The special function registers include the indirect ad-
dressing registers (R0;00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer registers (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
Watchdog Timer option setting register (WDTS;09H),
I/O registers (PA;12H, PB;14H, PC;16H, PG;1EH) and
I/O control registers (PAC;13H, PBC;15H, PCC;17H,
PGC;1FH). The remaining space before the 20H is re-
served for future expanded usage and reading these
locations will return the result
00H. The general pur-
pose data memory, addressed from 20H to 7FH, is used
for data and control information under instruction com-
mands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by
SET [m].i and
CLR [m].i. They are also indirectly accessible through
memory pointer registers (MP). The control register of
the EEPROM data memory is located at [40H] in Bank 1.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration on [00H] and [02H] access the RAM pointed to
by MP0 (01H) and MP1 (03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation. The
function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory in Bank 0, while MP1 can be applied to data
memory in Bank 0 and Bank1.
G e n e r a l P u r p o s e
D A T A M E M O R Y
( 9 6 B y t e s )
S p e c i a l P u r p o s e
D A T A M E M O R Y
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
7 F H
: U n u s e d
R e a d a s " 0 0 "
2 0 H
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
M P 0
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
M P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
I N T C
T M R
T M R C
P A
P A C
P B
P B C
P C
P C C
P G
P G C
8 0 H
F F H
RAM Mapping
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