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| 型号： | 48e30 |
| 厂商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit I/O Type MCU (With EEPROM) |
| 中文描述： | 8位I / O型微控制器（带EEPROM） |
| 文件页数： | 7/44页 |
| 文件大小： | 351K |
| 代理商： | 48E30 |
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HT48E30
Rev. 0.00
15
January 12, 2004
Preliminary
Input/Output Ports
There are 23 bidirectional input/output lines in the
microcontroller, labeled from PA to PC and PG, which
are mapped to the data memory of [12H], [14H], [16H]
and [1EH] respectively. All of these I/O ports can be
used for input and output operations. For input opera-
tion, these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruction
MOV
A,[m]
(m=12H, 14H, 16H or 1EH). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PGC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without pull-high resistor structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the con-
trol register must write a
1. The input source also de-
pends on the control register. If the control register bit is
1, the input will read the pad state. If the control regis-
ter bit is
0, the contents of the latches will move to the
internal bus. The latter is possible in the
read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 1FH.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by
SET [m].i and CLR [m].i (m=12H, 14H,
16H or 1EH) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i, CLR
[m].i
, CPL [m], CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the de-
vice. The highest 7-bit of port G are not physically imple-
mented; on reading them a
0 is returned whereas writing
then results in no operation. See Application note.
There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is se-
lected, the I/O line has a pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ sig-
nals, respectively. If the BZ/BZ option is selected, the
output signal in output mode of PB0/PB1 will be the PFD
signal generated by timer/event counter 0 overflow sig-
nal. The input mode always remain in its original func-
tions. Once the BZ/BZ option is selected, the buzzer
output signals are controlled by the PB0 data register
only.
The I/O functions of PB0/PB1 are shown below.
PB0 I/O
I
OO
O
OOOOO
PB1 I/O
I
O
I
OOOOO
PB0 Mode
x
C
B
C
BBBB
PB1 Mode
x
C
x
C
B
PB0 Data
x
D
0
1
D0
0101
PB1 Data
x
D
x
D1
DD
x
PB0 Pad Status
I
D
0
B
D0
0B0B
PB1 Pad Status
I
D
I
D1
DD
0
B
Note:
I input, O output, D, D0,D1 data,
B buzzer option, BZ or BZ, x don’t care
C CMOS output
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