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参数资料
| 型号： | 5962-0150601HXX |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封装： | CERAMIC, LCC-68 |
| 文件页数： | 14/20页 |
| 文件大小： | 3511K |
| 代理商： | 5962-0150601HXX |
REV. A
–3–
AD13465
Test
Mil
AD13465AZ/BZ
Parameter
Temp
Level
Sub-Group
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 4.98 MHz
25
°CV
85
dBFS
Analog Input @ 9.9 MHz
25
°CI
48086
dBFS
Full
II
5, 6
78
84
dBFS
Analog Input @ 21 MHz
25
°CI
46976
dBFS
Full
II
5, 6
68
74
dBFS
Analog Input @ 32 MHz
25
°CV
63
dBFS
Full
V
62
dBFS
SINGLE-ENDED ANALOG INPUT
Pass-Band Ripple to 10 MHz
25
°CV
0.05
dB
Pass-Band Ripple to 25 MHz
25
°CV
0.1
dB
DIFFERENTIAL ANALOG INPUT
Pass-Band Ripple to 10 MHz
25
°CV
0.3
dB
Pass-Band Ripple to 25 MHz
25
°CV
0.82
dB
TWO-TONE IMD REJECTION
10
fIN = 9.1 MHz and 10.1 MHz
25
°CI
4
75.5
82
dBc
f1 and f2 are –7 dB
Full
II
5, 6
74.5
80
fIN = 19.1 MHz and 20.7 MHz
25
°CV
72
dBc
f1 and f2 are –7 dB
CHANNEL-TO-CHANNEL ISOLATION
11
25
°CIV
12
90
dB
TRANSIENT RESPONSE
25
°CV
15.3
ns
DIGITAL OUTPUTS
12
Logic Compatibility
CMOS
DVCC = 3.3 V
Logic 1 Voltage
Full
I
1, 2, 3
2.5
DVCC – 0.2
V
Logic 0 Voltage
Full
I
1, 2, 3
0.2
0.5
V
DVCC = 5 V
Logic 1 Voltage
Full
V
DVCC – 0.3
V
Logic 0 Voltage
Full
V
0.35
V
Output Coding
Two’s Complement
POWER SUPPLY
AVCC Supply Voltage
13
Full
VI
4.85
5.0
5.25
V
I (AVCC) Current
Full
V
270
308
mA
AVEE Supply Voltage
13
Full
VI
–5.25
–5.0
–4.75
V
I (AVEE) Current
Full
V
38
49
mA
DVCC Supply Voltage
13
Full
VI
3.135
3.3
3.465
V
I (DVCC) Current
Full
V
34
46
mA
(Total) Supply Current per Channel
Full
I
1, 2, 3
369
403
mA
Power Dissipation (Total)
Full
I
1, 2, 3
3.57
3.9
W
Power Supply Rejection Ratio (PSRR)
Full
V
0.02
%FSR/%VS
NOTES
1 Gain tests are performed on AMP-IN-X-1 input voltage range.
2 Input capacitance spec. combines AD8037 capacitance and ceramic package capacitance.
3 Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4 For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180
° out of phase). For single ended input: +IN = 2 V p-p and –IN = GND.
5 All ac specifications tested by driving ENCODE and
ENCODE differentially. AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.
6 Minimum and Maximum conversion rates allow for variation in Encode Duty Cycle of 50%
± 5%.
7 Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).
Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale.
8 Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics.
Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale.
9 Analog Input signal power at –1 dBFS; SFDR is ratio of converter full scale to worst spur.
10 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
11 Channel-to-channel isolation tested with A Channel grounded and a full-scale signal applied to B Channel.
12 Digital output logic levels: DV
CC = 3.3 V, CLOAD = 10 pF. Capacitive loads > 10 pF will degrade performance.
13 Supply voltage recommended operating range. AV
CC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.
Specifications subject to change without notice.
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