- 您现在的位置：买卖IC网 > PDF目录67320 > 5962-0150601HXX (ANALOG DEVICES INC) DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 PDF资料下载
参数资料
| 型号： | 5962-0150601HXX |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | DUAL 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封装： | CERAMIC, LCC-68 |
| 文件页数： | 19/20页 |
| 文件大小： | 3511K |
| 代理商： | 5962-0150601HXX |
REV. A
AD13465
–8–
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential is
computed by rotating the inputs phase 180 degrees and taking
the peak measurement again. The difference is then computed
between both peak measurements.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic 1 state to achieve rated performance;
pulsewidth low is the minimum time the ENCODE pulse should
be left in low state. At a given clock rate, these specs define an
acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE command and the time when all output data bits are
within valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc. May be reported in dB
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. May be reported in
dB (i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic.
Transient Response
The time required for the converter to achieve 0.02% accuracy
when a one-half full-scale step function is applied to the analog
input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
tA
AIN
ENC,
ENC
D[13:0]
DRY
N
N+1
N+2
N+3
N+4
N
N+1
N+2
N+3
N+4
N–3
N–2
N–1
N
tENCL
tENCH
tENC
tE_DR
tOD
Figure 1. Timing Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| 5962-0251002HXC | 1-OUTPUT 8 W DC-DC REG PWR SUPPLY MODULE |
| 5962-9213902HZC | 1-OUTPUT 12 W DC-DC REG PWR SUPPLY MODULE |
| 5962-9555902HXC | 2-OUTPUT 12 W DC-DC REG PWR SUPPLY MODULE |
| 5962-9214402HXC | 2-OUTPUT 15 W DC-DC REG PWR SUPPLY MODULE |
| 5962-9213902HXC | 1-OUTPUT 12 W DC-DC REG PWR SUPPLY MODULE |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962015062963 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 5962015063140 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 5962015063593 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 5962015063695 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 5962015067534 | 制造商: 功能描述: 制造商:undefined 功能描述: |
发布紧急采购，3分钟左右您将得到回复。