- 您现在的位置：买卖IC网 > PDF目录67334 > 5962-9169101M3A (CRYSTAL SEMICONDUCTOR CORP) 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 PDF资料下载
参数资料
| 型号： | 5962-9169101M3A |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 封装： | LCC-28 |
| 文件页数： | 27/48页 |
| 文件大小： | 647K |
| 代理商： | 5962-9169101M3A |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
CH1/2 - Left/Right Input Channel Select, PIN 13.
Status at the end of a conversion cycle determines which analog input channel will be acquired
for the next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate
which channel is being sampled during the current acquisition phase.
SLEEP - Sleep, PIN 28.
When brought low causes the CS5101A or CS5102A to enter a power-down state. All
calibration coefficients are retained in memory, so no recalibration is needed after returning to
the normal operating mode. If using the internal crystal oscillator, time must be allowed after
SLEEP returns high for the crystal oscillator to stabilize. SLEEP should be tied high for normal
operation.
CODE - 2’s Complement/Binary Coding Select, PIN 16.
Determines whether output data appears in 2’s complement or binary format. If high, 2’s
complement; if low, binary.
BP/UP - Bipolar/Unipolar Input Range Select, PIN 17.
When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF.
When high, the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.
SCKMOD - Serial Clock Mode Select, PIN 27.
When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with
OUTMOD to select one of 4 output modes described in Table 2.
OUTMOD - Output Mode Select, PIN 18.
The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The
four modes are described in Table 2.
SCLK - Serial Clock, PIN 14.
Serial data changes status on a falling edge of this input, and is valid on a rising edge. When
SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A
generates its own serial clock at one-fourth the master clock frequency and SCLK is an output.
RST - Reset, PIN 2.
When taken low, all internal digital logic is reset. Upon returning high, a full calibration
sequence is initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN
cycles (CS5102A) to complete. During calibration, the HOLD input will be ignored. The
CS5101A or CS5102A must be reset at power-up for calibration, however; calibration is
maintained during SLEEP mode, and need not be repeated when resuming normal operation.
Analog Inputs
AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24.
Analog input connections for the left and right input channels.
VREF - Voltage Reference, PIN 20.
The analog reference voltage which sets the analog input range. In unipolar mode VREF sets
full-scale; in bipolar mode its magnitude sets both positive and negative full-scale.
CS5101A CS5102A
DS45F2
33
相关PDF资料 |
PDF描述 |
|---|---|
| 5962-9169201MXA | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 5962-9169201Q3C | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 5962-9169201QXC | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 5962-9169301MCA | 4 CHANNEL, VIDEO AMPLIFIER, CDIP14 |
| 5962-9169401MCA | 1 CHANNEL, VIDEO AMPLIFIER, CDIP14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962-9169301M2A | 制造商:Texas Instruments 功能描述:-LIFETIME BUYS TIL 03/03 |
| 5962-9169701MMA | 制造商:e2v Aerospace & Defense 功能描述:SMD MKD 87C51RC-16 PHI-JLCC |
| 5962-9169701MUA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| 5962-9169702MUA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-9172201MEA | 制造商:e2v 功能描述:Counter Single 4-Bit Binary UP 16-Pin CDIP 制造商:e2v technologies 功能描述:Counter Single 4-Bit Binary UP 16-Pin CDIP |
发布紧急采购，3分钟左右您将得到回复。