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| 型号： | 5962-9169101M3A |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 封装： | LCC-28 |
| 文件页数： | 36/48页 |
| 文件大小： | 647K |
| 代理商： | 5962-9169101M3A |
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Control Signals
Figure 5 shows 2 headers are provided for serial
data output and control signals. JP3 provides
SDATA and SSH/SDL outputs. It also allows ac-
cess to SCLK & CH1/CH2 which may be inputs
or outputs depending on the serial mode selected
by the DIP switches. Jumpers J10, J11, J12, &
J13 must be set to correspond with the appropri-
ate directions of SCLK and CH1/CH2.
JP5 provides output only access to the +5V logic
supply, SCLK, SDATA and SLATCH, the serial
to parallel latching control.
Serial to Parallel Conversion
When operating in the FRN or SSC serial port
modes, the CS5101A/02A readily provides the
three signals (SCLK, SDATA, and SSH/SDL) to
support serial to parallel conversion of its output
data.
Figure 6 Shows 2 74HC595’s provided to con-
vert the serial output of the ADC to parallel. A
handshake flip-flop, U3, is provided for the par-
allel interface if required. When parallel data is
available to read, DRDY goes low. The com-
puter reads the data and sets DACK high and
then low. This resets the flip-flop for the next
word. JP4 selects whether both CH1 and CH2
data appears alternately, or CH1 only, or CH2
only.
SCLK
Direction
J10
In
Out
JP3
J11
J12
OE1
OE2
Y0
Y1
Y2
Y3
Y4
Y5
74HC365
3
5
7
9
11
13
2
4
6
10
12
14
1
15
U12
.1
F
C48
+5V
Out
In
A0
A1
A2
A3
A4
A5
R32
68
HDR5D
HDR10D
+5V
JP5
10
R3
+
C47
10
F
R33
68
SSH/SDL
SDATA
SCLK
SLATCH
CH1/CH2
J13
Direction
CH1/CH2
SDATA
SCLK
SSH/SDL
CH1/CH2
+5V
SLATCH
SCLK
SDATA
Fig. 4
Fig. 6
Figure 5. Serial Output Buffers
CDB5101A/5102A
DS45DB3
41
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