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参数资料
| 型号： | 5962D0053605QYX |
| 元件分类： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 20 ns, CDFP36 |
| 封装： | CERAMIC, DFP-36 |
| 文件页数： | 10/16页 |
| 文件大小： | 138K |
| 代理商： | 5962D0053605QYX |
3
WRITE CYCLE
A combination of W less than VIL(max) and E less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when W is less
than VIL(max).
Write Cycle 1, the Write Enable - Controlled Access in figure
5a, is defined by a write terminated by W going high, with E
still active. The write pulse width is defined by tWLWH when the
write is initiated by W, and by tETWH when the write is initiated
by E. Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait tWLQZ before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable - Controlled Access in figure
5b, is defined by a write terminated by E going inactive. The
write pulse width is defined by tWLEF when the write is initiated
by W, and by tETEF when the write is initiated by the E going
active. For the W initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait tWLQZ before applying data to the eight bidirectional
pins DQ(7:0) to avoid bus contention.
OPERATIONAL ENVIRONMENT
Table 2. Operational Environment
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Adam’s 0% worst case environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose
50
krad(Si)
Heavy Ion
Error Rate2
<1.1E-9
Errors/Bit-Day
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