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参数资料
| 型号： | 5962D0153301QXX |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, QMA68 |
| 封装： | DUAL CAVITY, CERAMIC, QFP-68 |
| 文件页数： | 13/14页 |
| 文件大小： | 124K |
| 代理商： | 5962D0153301QXX |
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
(-40
°C to +125°C) (V
DD = 3.3V + 0.3)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 101 9.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 300mV change from steady-state output voltage .
SYMBOL
PARAMETER
MIN
MAX
UNIT
tAVAV
1
Write cycle time
35
ns
t
ETWH
Device Enable to end of write
20
ns
tAVET
Address setup time for write (En - controlled)
0
ns
tAVWL
Address setup time for write (Wn - controlled)
0
ns
tWLWH
Write pulse width
20
ns
t
WHAX
Address hold time for write (Wn - controlled)
2
ns
tEFAX
Address hold time for Device Enable (En - controlled)
2
ns
t
WLQZ
2
Wn- controlled three-state time
10
ns
tWHQX
2
Wn - controlled Output Enable time
5
ns
t
ETEF
Device Enable pulse width (En - controlled)
20
ns
tDVWH
Data setup time
15
ns
t
WHDX
2
Data hold time
2
ns
tWLEF
Device Enable controlled write pulse width
20
ns
t
DVEF
2
Data setup time
15
ns
tEFDX
Data hold time
2
ns
tAVWH
Address valid to end of write
20
ns
tWHWL
1
Write disable time
5
ns
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