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参数资料
| 型号： | 5962D0153301QXX |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, QMA68 |
| 封装： | DUAL CAVITY, CERAMIC, QFP-68 |
| 文件页数： | 8/14页 |
| 文件大小： | 124K |
| 代理商： | 5962D0153301QXX |
3
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when eitherG is greater than V
IH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by tWLWH when the write is
initiated byWn, and by tETWH when the write is initiated byEn.
Unless the outputs have been previously placed in the high-
impedance state byG, the user must wait t
WLQZ before applying
data to the eight bidirectional pins DQn(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait t
WLQZ before applying data to the eight
bidirectional pins DQn(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT8Q512K32 SRAM incorporates features which allow
operation in a limited radiation environment.
Table 2. Typical Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose
50
krad(Si) nominal
Heavy Ion
Error Rate 2
3.8E-11
Errors/Bit-Day
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