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参数资料
| 型号： | 5962D0153301QXX |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 MULTI DEVICE SRAM MODULE, 35 ns, QMA68 |
| 封装： | DUAL CAVITY, CERAMIC, QFP-68 |
| 文件页数： | 7/14页 |
| 文件大小： | 124K |
| 代理商： | 5962D0153301QXX |
2
PIN NAMES
DEVICE OPERATION
Each die in the UT8Q512K32 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes I
DD to rise to its active value, and decodes the 19 address
inputs to each memory die by selecting the 2,048,000 byte of
memory. Wn controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than V IH (min) withEn and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQn(7:0)
after the specified t
AVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (t AVAV).
SRAM read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t
ETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQn(7:0).
SRAM read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0)
Address
Wn
WriteEnable
DQ(7:0)
Data Input/Output
G
Output Enable
En
Device Enable
V
DD
Power
V
SS
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Top View
DQ0(0)
DQ1(0)
DQ2(0)
DQ3(0)
DQ4(0)
DQ5(0)
DQ6(0)
DQ7(0)
VSS
DQ0(1)
DQ1(1)
DQ2(1)
DQ3(1)
DQ4(1)
DQ5(1)
DQ6(1)
DQ7(1)
DQ0(2)
DQ1(2)
DQ2(2)
DQ3(2)
DQ4(2)
DQ5(2)
DQ6(2)
DQ7(2)
VSS
DQ0(3)
DQ1(3)
DQ2(3)
DQ3(3)
DQ4(3)
DQ5(3)
DQ6(3)
DQ7(3)
N
C
A
0
A
1
A
2
A
3
A
4
A
5
E
2
V
S
E
3
W
0
A
6
A
7
A
8
A
9
A
1
0
V
D
V
D
A
1
A
1
2
A
1
3
A
1
4
A
1
5
A
1
6
E
0
G
E
1
A
1
7
W
1
W
2
W
3
A
1
8
N
C
N
C
Figure 2. 25ns SRAM Pinout (68)
G
Wn
En
I/O Mode
Mode
X
1
X
1
3-state
Standby
X
0
Data in
Write
1
0
3-state
Read
2
0
1
0
Data out
Read
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