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| 型号： | 5962R9855202QYC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 21/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962R9855202QYC |
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28
Read the ICS register with an Input Register Instruction INR
Rd,ICS before interrupts are re-enabled or before executing a
program branch to assure that the return address in the ICS is
not overwritten. The CALL instruction saves the IC into the
ICS register and overwrites the interrupt return address with
the CALL return address. Similarly, if the interrupts are re-
enabled before the interrupt return address is read from the ICS,
the occurrence of a new interrupt causes the old return address
to be overwritten. It is suggested for CALL instructions the
software reserve register pair xR16 for ICS storage; for
interrupts the software reserve register pair xR18 for ICS
storage. When nested CALLs or interrupts are encountered, the
address values stored in register pairs xR16 and xX18,
respectively, must be stored in system memory to provide the
UT69R000 with full return information.
6.2 Interrupt Sources
Interrupt sources include nine externally generated hardware
interrupts, two internally generated hardware interrupts, and
four internally generated software interrupts. External
interrupts include: INT(6:0), MCHNE(2:1), PFAIL, BTERR,
MPROT, and MPAR. Internal hardware interrupts include
TIMA and TIMB. Software interrupts include USR(3:1) and
FIPO.
User-defined hardware interrupts INT(6:0) are available to
signal the occurrence of events which require special action by
the UT69R000. User-defined interrupts are entered into PI
Register bits 2, 8, 10, 11, 12, 13, and 14. Internal hardware
interrupts TIMA and TIMB signal the wrap-around of either
of these 16-bit counters from FFFF (hex) to 0000 (hex).
Machine error interrupts MCHNE(2:1), BTERR, MPROT, and
MPAR designate machine error interrupts. The UT69R000
enters machine error interrupts into the Fault Register, the
logical OR of all Fault Register bits generates the stimulus to
control bit 14 of the PI Register. On the occurrence of a
Machine Error Interupt the host examines the Fault Register to
determine the specific event that generated the interrupt. Input
Register and Output Register Instructions INR Rd,FT, OTR
Rd,FT, and OTR Rd,RFT read, write, and clear the Fault
Register. Clear the Fault Register before clearing the PI
Register.
Generate software interrupts by executing an Output Register
Instruction OTR Rd,PI. User-defined software interrupts
include USR3, USR2, and USR1. A fourth software interrupt
includes FIPO, fixed-point overflow. When enabled and not
masked interrupt FIPO signals the assertion of condition code
bit V to a logical one. Generate user-defined interrupt USR3,
USR2, and USR1 by writing to the PI Register. Please note;
clear the specific bit in the PI Register before attempting to
generate a software interrupt.
6.3 Interrupt Hardware
All the UT69R000 external interrupts are level triggered.
Interrupts INT(6:0) and PFAIL are sampled on the rising edge
of the OSCIN and latched into the PI Register on the falling
edge of STATE1 (rising edge of CK1). The minimum pulse
width for these inputs is 500 ns.
Machine error interrupts MCHNE(2:1), BTERR, MPAR, and
MPROT provide stimulus to the PI Register through an S-R
flip-flop. The architecture requires removal of the interrupt
signal before the Fault Register (FT) and PI Register can be
cleared. If the FT and PI Register is cleared while the interrupt
input is asserted the specific FT and PI Register bit is re-
asserted.
6.4 Interrupt Latency
Figures 24, 25, and 26 display the latency associated with
servicing of interrupts. When an interrupt is sampled into the
UT69R000 before the falling edge of STATE1 (figure 24)
interrupt service begins during the following execute machine
cycle (STATE1 low). If the interrupt is sampled into the
UT69R000 after the falling edge of STATE1 (figure 26)
interrupt service is delayed one execution cycle. Interrupts are
first sampled into the device and then latched into the PI
Register.
When the interrupt is latched coincident with the fetch and
execution of a CALL instruction the interrupt latency increases.
Figure 25 shows interrupt latency associated to the CALL
instruction. The increase in interrupt latency is due to the
temporary disable of the latching of interrupts into the PI
register. This temporary disable is due to the fetch of the CALL
instruction. The disable is necessary to allow for the UT69R000
to execute the CALL instruction before servicing the
interrupt.7.0 Monitor
7.0 Monitor
Communication between the UT69R000 and a dumb terminal
or IRSIM is established via a monitor program written to
support the internal UART. When operating in the monitor
mode the programmer can (1) examine and modify the
UT69R000’s internal registers; (2) examine and modify the
contents of the operand port memory; (3) examine and modify
the contents of I/O subsystems; (4) control program execution.
UTMC offers a monitor shell program for the UT69R000. The
software programmer can tailor the monitor program to meet
specific application.
Assertion of a discrete input can signal the UT69R000 to enter
the monitor mode of operation. To perform this function the
application software polls the Status Register looking for the
assertion (i.e., transition to logic one) of the appropriate
discrete input. The UT69R000 then enters the monitor program
via a CALL or BR instruction. Interrupts can also be used to
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