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参数资料
| 型号： | 5962R9855202QYC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 8/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962R9855202QYC |
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16
Instruction Counter and Instruction Register
The UT69R000’s instruction port interface consists of a 20-bit
instruction address and a 16-bit data bus. The Instruction
Counter (IC) supplies the 20-bit address to memory. The
instruction read from memory is then stored into the Instruction
Register (IR, 16-bits wide). The IR consists of two sets of
internal latches, a Primary Instruction Register latch (PIR, 16-
bits wide) and the Instruction Register latch (IRL, 16-bits
wide). These two sets of latches allow the UT69R000 to
perform overlapping memory fetch and execute cycles. This
means the UT69R000 performs a delayed branch when the flow
of the program is interrupted. A delayed branch implies that
the UT69R000 fetches and executes the instruction following
the branch condition before the UT69R000 executes the first
instruction at the branch location.
Instruction Counter Save Register
The UT69R000 uses the Instruction Counter Save Register
(ICS) when servicing interrupts and branch instructions. When
an interrupt or branch occurs, the UT69R000 saves the IC in
the ICS. Read the ICS immediately after entering the target
routine to save the return location before any other IC save
occurs. The UT69R000 reads the ICS using input instruction
INR XRd, ICS. Please note that the ICS read requires a 32-bit
wide register.
Timer A and Timer B
Timer A and B registers are 16-bit binary counters. Input/output
instructions start, halt, read, and write these counters. Timer A
resolution is 10
s per bit, Timer B has a resolution of 100s
per bit (TIMCLK at 12 MHz). Each timer generates a time-out
interrupt when the counter transitions from FFFF (hex) to 0000
(hex). Time intervals before interrupt are defined as the
difference between the loaded value and 0000 (hex). For
example, load Timer A with the value FFFE (hex), start Timer
A; an interrupt occurs 20
s later as the timer transitions from
FFFF (hex) to 0000 (hex). The Pending Interrupt Register
reflects this time-out condition.
Modify the resolution of Timer A and B by scaling the
TIMCLK input. For example, to decrease Timer A resolution
from 10
s to 64s per bit, TIMCLK is decreased to 1.88 MHz.
3.0 Instruction Port
Instruction port signals include a 20-bit address bus RA(19:0),
a 16-bit data bus RD(15:0), and two control signals OE and
WE. During instruction and data fetch cycles, OE is asserted
(WE negated). Write operations to the port asserts WE and
negates OE. Primarily designed for fast access of instruction
information, the instruction port does not allow for the
inclusion of wait states.
The UT69R000 divides all operations into four distinct time
periods (CK1 through CK4). These time periods are based on
the processor clock. The UT69R000 performs a separate
function during each of these four time periods.
During CK1, the UT69R000 begins executing the instruction
in the Primary Instruction Register (PIR). The instruction
executed is the instruction the UT69R000 fetched during the
previous bus cycle. Also during CK1, the instruction address
for the next instruction to fetch from memory becomes valid.
(Thus, the overlapping fetch and execute cycles of the
UT69R000.) STATE1 output goes low, indicating the
UT69R000 is executing an instruction.
The UT69R000 begins variable width clock period CK2 after
completing CK1. For 2 and 3 clock cycle instructions CK2
remains one-half clock cycle in length. During four clock cycle
instructions CK2 is stretched to one and a half clock cycles.
The following conditions extend time period CK2: (1)
Executing a STRI instruction, (2) Executing a LRI instruction,
or (3) Executing any instruction access to the operand port. The
UT69R000 also extends clock period CK2 for the Operand Port
arbitration process. The UT69R000 samples the logical AND
combination of BUSY and inverted BGNT during CK2. If this
combination is low, time period CK2 extends until the
combination of the two signals is high, indicating the
UT69R000 now controls the Operand Port. STATE1 output
remains low for the entire CK2 time period.
At the beginning of CK3, STATE1 goes high indicating the
next instruction is being fetched from memory. The
UT69R000’s operand address and data buses become active at
the beginning of CK3 along with the Bus Grant Acknowledge
(BGACK), M/IO, and R/WR signals. Data Strobe (DS) asserts
one clock cycle after the beginning of CK3, one and a half clock
cycles after the start of CK4.
Following CK3 is variable length clock period CK4. The
stretch of CK4 occurs during the following instruction
executions: (1) Executing a STRI instruction, (2) Executing a
LRI instruction, (3) Executing any instruction with Long
Immediate data (e.g., MOV Rd, FFFFh), or (4) Executing any
operand port access. After time period CK4 starts, the
transparent latches that make up the Primary Instruction
Register enable, allowing the UT69R000 to input the
instruction from memory.
相关PDF资料 |
PDF描述 |
|---|---|
| 5962R9855202VZA | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962F9651601VCX | AC SERIES, HEX 1-INPUT INVERT GATE, CDIP14 |
| 5962F9651601VXX | AC SERIES, HEX 1-INPUT INVERT GATE, CDFP14 |
| 5962F9654501VXC | ACT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP16 |
| 5962F9656101QXX | ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDFP16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962R9863601VGA | 制造商:Analog Devices 功能描述: |
| 5962R9863602VGA | 制造商:Analog Devices 功能描述:OP AMP, JFET-INPUT - Rail/Tube |
| 5962R9863701VGA | 制造商:Analog Devices 功能描述:- Rail/Tube |
| 5962R9863701VHA | 制造商:Analog Devices 功能描述:AEROSPACE LOW INPUT CURRENT OPERATIONAL AMPLIFIER - Rail/Tube |
| 5962R9863701VPA | 制造商:Analog Devices 功能描述:OP AMP, GENERAL PURPOSE - Rail/Tube |
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