参数资料
型号: 71M6511-DB
厂商: Maxim Integrated Products
文件页数: 113/115页
文件大小: 0K
描述: BOARD DEMO 71M6511 ENERGY METER
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: 71M6511
已供物品: 2 个板,线缆,CD,电源
71M6511/71M6511H Demo Board User’s Manual
4.13 TERIDIAN 71M6511/6511H PIN-OUT INFORMATION
Power/Ground/NC Pins :
Name
GNDA
GNDD
V3P3A
V3P3D
VBAT
V2P5
VLCD
Pin #
49, 58
1
50
9
46
47
62
Type
P
P
P
P
P
O
P
Description
Analog ground: This pin should be connected directly to the ground plane.
Digital ground: This pin should be connected directly to the ground plane.
Analog power supply: A 3.3V power supply should be connected to this pin.
Digital power supply: A 3.3V power supply should be connected to this pin.
Battery backup power supply. A battery or super-capacitor is to be connected
between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D.
Output of the internal 2.5V regulator. This pin should be bypassed to GND with a
0.1μF capacitor
LCD power supply.
Analog Pins:
Name
IA
VA
IB
Pin #
54
51
53
Type
I
I
I
Description
Line Current Sense Input: This pin is a voltage input to the internal A/D converter.
Typically, it is connected to the output of a current transformer.
Line Voltage Sense Input: This pin is a voltage input to the internal A/D converter.
Typically, it is connected to the output of a resistor divider.
Line Current Sense Input: This pin is a voltage input to the internal A/D converter.
Typically, it is connected to the output of a current transformer.
For normal operation, a voltage of 2.6V to 2.8V has to be supplied to this pin. A
V1
56
I
voltage below VBIAS will reset the chip. Clamping V1 to V3P3 will disable the hard-
ware watchdog timer.
VREF
VBIAS
XIN
XOUT
VDRV
55
52
59
61
7
O
O
I
O
Voltage Reference for the ADC. A 0.1μF capacitor to GNDA should be connected
to this pin.
The reference voltage used by the power fault detection circuit.
Crystal Inputs: A 32kHz style crystal should be connected across these pins.
Typically, a 10pf capacitor is also connected from each pin to GNDA. It is
important to minimize the capacitance between these pins. See crystal
manufacturer datasheet for details.
Voltage boost output.
Table 4-6: 71M6511 Pin Description Table 1/2
Revision 5.4
? 2005-2007 TERIDIAN Semiconductor Corporation
Page: 113 of 115
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