参数资料
型号: 71M6511-DB
厂商: Maxim Integrated Products
文件页数: 74/115页
文件大小: 0K
描述: BOARD DEMO 71M6511 ENERGY METER
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: 71M6511
已供物品: 2 个板,线缆,CD,电源
71M6511/71M6511H Demo Board User’s Manual
Item #
in
Figure
3.2/3.3
19
20
Schematic &
PCB Silk
Screen
Reference
TP13, TP14
J3
Name
GND
IA_IN
Use
Ground test points.
3-pin header on the bottom of the board for connection of the CT for
phase A. Pin 3 may be used to ground an optional cable shield. In
shunt configuration, two wires from the shunt resistor representing
the voltage across the shunt are connected to pins 1 and 2.
21
J16
IB_IN
3-pin header on the bottom of the board for connection of the CT for
phase B. Pin 3 may be used to ground an optional cable shield.
22
J4
LIVE
This is the line voltage input that feeds both the resistor divider
leading to the VA pin on the chip and the internal power supply. The
line voltage wire is connected to the spade terminal on the bottom of
the board.
Caution: High Voltage. Do not touch this pin!
23
TP2
V3P3, VA
2-pin header test point. Pin 1 is the VA line voltage input to the IC,
pin 2 is V3P3.
24
JP1
2-pin header. When a jumper is installed, the on-board power
supply (AC signal) is used to power the Demo Board. When not
installed, the board must be powered by an external supply
connected to J1. Normally installed.
25
SW2
RESET
Chip reset switch: The RESTZ pin has an internal pull up that allows
normal chip operation. When the switch is pressed, the RESTZ pin
is pulled low which resets the IC into a known state.
26
J9
NEUTRAL
This is the NEUTRAL line voltage input. It is connected to the 3.3V
net of the 71M6511/71M6511H. The neutral wire is connected to the
spade terminal on the bottom of the board.
27
28
TP15
JP4
GND
SHUNT I/O
Ground test point.
3-pin header on the bottom side of the board. A wire from the shunt
resistor connects to pin 2, while an optional shield can be connected
to pin 3. When operating in CT mode, a jumper is plugged across
pins 1 and 2.
Table 3-6: 71M6511 2-Layer Demo Board Description: 2/3
Table 3-7 summarizes the jumper settings required for CT operation (factory default).
Jumper
Header
JP1
JP8
JP9
JP10
JP4
JP17
J13
TP10
Default Setting
Installed
V3P3-VBAT
1-2
5V-VLCD
1-2
Installed
V1IN-V3P3
V1-V3P3
Function in Default (Factory) Setting
Enables the internal power supply
Terminates the VBAT input properly when no battery is used.
Enables read and write operations for the EEPROM (U5)
Selects 5V supply provided by the VLCD driver for LCD operation.
Enables function of the Demo Board in CT mode
Enables function of the Demo Board in CT mode
Provides V3P3 to the V1 pin.
Provides V3P3 to the voltage divider used for V1 pin.
Table 3-7: Jumper Default Settings
Page: 74 of 115
? 2005-2007 TERIDIAN Semiconductor Corporation
Revision 5.4
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