参数资料
型号: 71M6511-DB
厂商: Maxim Integrated Products
文件页数: 73/115页
文件大小: 0K
描述: BOARD DEMO 71M6511 ENERGY METER
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: 71M6511
已供物品: 2 个板,线缆,CD,电源
71M6511/71M6511H Demo Board User’s Manual
3.2
Item #
2-LAYER BOARD DESCRIPTION: JUMPERS, SWITCHES, TEST
POINTS
Jumpers, headers, and connectors are largely identical for the two versions of the 2-Layer Demo Boards
(capacitive and transformer power supply).
The items described in the following tables refer to the flags in Figure 3-2 and Figure 3-3.
Schematic &
(Figure
3.2/3.3)
1
2
3
4
5
6
7
8
PCB Silk
Screen
Reference
J1
D5
D6
TP22
J2
TP21
J12
JP8
Name
5 Volt supply
WATTS
VARS
VARS
DEBUG
WATTS
V3P3, OPT_TX,
V3P3,
OPT_RX, GND
V3P3, VBAT,
GND
Use
Plug for connection of the external 5 VDC power supply.
LED emitting WATT pulses.
LED emitting VAR pulses.
Test points for pulses generated by the VARS LED.
Debug Board connector. 2x8 pin header.
Test points for pulses generated by the WATTS LED.
5-pin header. Pins 1 and 3 carry the supply voltage to the 6511 IC.
Pin 2 is the TX_OPT output of the 6511 IC. Pin 4 is the OPT_RX
input to the 6511 IC. Pin 5 is ground.
3-pin header for connection of a 3.6V battery. The battery is
connected to pin 2 (+) and pin 3 (-). If no battery is used, a jumper is
plugged over pins 1 and 2.
9
JP17
SHUNT I/O
2-pin header. In CT mode, a jumper must be plugged into JP17. In
shunt mode, one wire from the shunt resistor is connected to pin 1.
10
TP17
TMUXOUT,
2-pin header providing test points for TMUXOUT and CKTEST.
CKTEST
11
12
13
14
JP10
TP20
J14
TP10
V3P3, VLCD,
5V
SSI
EMULATOR I/F
V1, V3P3
3-pin header for selecting the VLCD voltage. Pin 3 is 5V and pin 1 is
3.3V. The default setting for the jumper is 5V.
5x2 header. High-speed serial interface. One row is ground.
2x10 emulator connector port for Signum ICE ADM-51.
2-pin header representing the V1 comparator voltage input test
point and ground. A jumper should be placed between V1 and V3P3
to disable the watchdog timer.
15
J13
V3P3, V1IN
2-pin header. A jumper should be placed between V1IN and V3P3
to supply 3.3V to the resistor divider generating V1.
16
TP7
GND,
2-pin header. Pin 2 is ground; pin 1 is the VREF output of the IC.
VREFOUT
17
TP19
IB
2-pin header test point. Pin is the IB input to the IC and the other
pin is V3P3.
18
TP1
IA
2-pin header test point. Pin is the IA input to the IC and the other
pin is V3P3.
Table 3-5: 71M6511 2-Layer Demo Board Description: 1/2
Revision 5.4
? 2005-2007 TERIDIAN Semiconductor Corporation
Page: 73 of 115
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