参数资料
型号: 71M6511-DB
厂商: Maxim Integrated Products
文件页数: 46/115页
文件大小: 0K
描述: BOARD DEMO 71M6511 ENERGY METER
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: 71M6511
已供物品: 2 个板,线缆,CD,电源
71M6511/71M6511H Demo Board User’s Manual
From the voltage measurement, we determine that
1.
A XV = E V + 1
We use the other two measurements to determine φ S and A XI .
2.
E 0 =
IV A XV A XI cos( 0 ? φ S )
IV cos( 0 )
? 1 = A XV A XI cos( φ S ) ? 1
2a.
A XV A XI =
E 0 + 1
cos( φ S )
3.
E 60 =
IV A XV A XI cos( 60 ? φ S )
IV cos( 60 )
? 1 = A XV A XI
cos( 60 ? φ S )
cos( 60 )
? 1
3a.
E 60 =
A XV A XI [ cos( 60) cos( φ S ) + sin( 60) sin( φ S ) ]
cos( 60 )
? 1
= A XV A XI cos( φ S ) + A XV A XI tan( 60 ) sin( φ S ) ? 1
Combining 2a and 3a:
4.
E 60 = E 0 + ( E 0 + 1 ) tan( 60 ) tan( φ S )
5.
tan( φ S ) =
E 60 ? E 0
( E 0 + 1 ) tan( 60 )
? ?
φ S = tan ? 1 ? ?
6.
? E 60 ? E 0 ?
? ( E 0 + 1 ) tan( 60 ) ?
and from 2a:
7.
A XI =
E 0 + 1
A XV cos( φ S )
Now that we know the A XV , A XI , and φ S errors, we calculate the new calibration voltage gain coefficient from
the previous ones:
CAL _ V NEW =
CAL _ V
A XV
? tan( φ S ) 1 + ( 1 ? 2 ? 9 ) 2 ? 2 ( 1 ? 2 ? 9 ) cos( 2 π f 0 T ) ] ?
PHADJ = 2 ?
[
]
?
? ( 1 ? 2 ) sin( 2 π f 0 T ) ? tan( φ S ) 1 ? ( 1 ? 2 ) cos( 2 π f 0 T ) ?
We calculate PHADJ from φ S , the desired phase lag:
20
? 9 ? 9
Page: 46 of 115
? 2005-2007 TERIDIAN Semiconductor Corporation
Revision 5.4
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