- 您现在的位置：买卖IC网 > PDF目录68812 > 71M6543GH-IGTR/F (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY ANALOG CIRCUIT, PQFP100 PDF资料下载
参数资料
| 型号： | 71M6543GH-IGTR/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, LQFP-100 |
| 文件页数： | 89/157页 |
| 文件大小： | 2178K |
| 代理商： | 71M6543GH-IGTR/F |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页当前第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页
71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
37
Table 18: UART Modes
UART 0
UART 1
Mode 0
N/A
Start bit, 8 data bits, parity, stop bit, variable
baud rate (internal baud rate generator)
Mode 1
Start bit, 8 data bits, stop bit, variable
baud rate (internal baud rate generator
or timer 1)
Start bit, 8 data bits, stop bit, variable baud
rate (internal baud rate generator)
Mode 2
Start bit, 8 data bits, parity, stop bit,
fixed baud rate 1/32 or 1/64 of fCKMPU
N/A
Mode 3
Start bit, 8 data bits, parity, stop bit,
variable baud rate (internal baud rate
generator or timer 1)
N/A
Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of
8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant 1.
8-bit serial modes with parity can be simulated by setting and reading the 9
th bit, using the control
bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B) registers
for transmit and RB81 (S1CON[2]) for receive operations.
All supported operation modes use oversampling for the incoming bit stream when receiving data. Each
bit is sampled three times at the projected middle of the bit duration. This technique allows for deviations
of the received baud rate from nominal of up to 3.5%.
The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals
for inter-processor communication in multi-processor systems. In this case, the slave processors have bit
SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs
the slave’s address, it sets the 9
th bit to 1, causing a serial port receive interrupt in all the slaves. The slave
processors compare the received byte with their address. If there is a match, the addressed slave clears
SM20 or SM21 and receive the rest of the message. The rest of the slaves ignore the message. After
addressing the slave, the host outputs the rest of the message with the 9
th bit set to 0, so no additional
serial port receive interrupts is generated.
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except
for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to
ignore ones written to them.
Table 19: The S0CON (UART0) Register (SFR 0x98)
Bit
Symbol
Function
S0CON[7]
SM0
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
S0CON[6]
SM1
S0CON[5]
SM20
Enables the inter-processor communication feature.
S0CON[4]
REN0
If set, enables serial reception. Cleared by software to disable reception.
相关PDF资料 |
PDF描述 |
|---|---|
| 71M6543GH-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6543G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 722BG | 2-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 722MG | 2-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 73M1903-IGV | SPECIALTY CONSUMER CIRCUIT, PQFP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6543GHT-IGT/F | 制造商:Maxim Integrated Products 功能描述:3-PHASE, 128KB, PRES TEMP SENSOR, HI PREC - Bulk |
| 71M6543GHT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:3-PHASE, 128KB, PRES TEMP SENSOR, HI PREC - Tape and Reel |
| 71M6543G-IGT/F | 功能描述:计量片上系统 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6543G-IGTR/F | 功能描述:计量片上系统 - SoC Precision Energy Meter IC RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 处理器系列:71M6511 类型:Metering SoC 最大时钟频率:70 Hz 程序存储器大小:64 KB 数据 RAM 大小:7 KB 接口类型:UART 可编程输入/输出端数量:12 片上 ADC: 安装风格:SMD/SMT 封装 / 箱体:LQFP-64 封装:Reel |
| 71M6543GT-IGT/F | 制造商:Maxim Integrated Products 功能描述:3-PHASE, 128KK, PRES TEMP SENSOR - Bulk |
发布紧急采购，3分钟左右您将得到回复。