- 您现在的位置：买卖IC网 > PDF目录294128 > 72V275L15PF8 (INTEGRATED DEVICE TECHNOLOGY INC) 32K X 18 OTHER FIFO, 10 ns, PQFP64 PDF资料下载
参数资料
| 型号： | 72V275L15PF8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 32K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 封装： | PLASTIC, TQFP-64 |
| 文件页数： | 2/25页 |
| 文件大小： | 266K |
| 代理商： | 72V275L15PF8 |
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFOTM
32,768 x 18 and 65,536 x 18
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAE and PAF values can be achieved by using a
combination of the
LD, SEN, WCLK and SI input pins. Programming PAE
and
PAFproceedsasfollows: whenLDandSENaresetLOW,dataonthe
SI input are written, one bit for each WCLK rising edge, starting with the Empty
Offset LSB and ending with the Full Offset MSB. A total of 30 bits for the
IDT72V275 and 32 bits for the IDT72V285. See Figure 13, Serial Loading of
Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete
set of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI input
andthen,bybringing
LDandSENHIGH,datacanbewrittentoFIFOmemory
via Dn by toggling
WEN. When WEN is brought HIGH with LD and SEN
restored to a LOW, the next offset bit in sequence is written to the registers via
SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset
LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. Once
LD and SEN are both restored to a LOW level, serial offset programming
continues.
Fromthetimeserialprogramminghasbegun,neitherpartialflagwillbevalid
until the full set of bits required to fill all the offset registers has been written.
Measuring from the rising WCLK edge that achieves the above criteria;
PAF
will be valid after two more rising WCLK edges plus tPAF,
PAE will be valid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programming of
PAE and PAF values can be achieved by using a
combinationofthe
LD, WCLK,WENandDninputpins. ProgrammingPAE
and
PAF proceeds as follows: when LD and WEN are set LOW, data on
theinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW-to-HIGH
transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, data
arewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLKwrites,once
again, to the Empty Offset Register. See Figure 14, Parallel Loading of
Programmable Flag Registers, for the timing diagram for this mode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing
LD HIGH, write operations can be redirected to
the FIFO memory. When
LD is set LOW again, and WEN is LOW, the next
offsetregisterinsequenceiswrittento.Asanalternativetoholding
WENLOW
and toggling
LD,parallelprogrammingcanalsobeinterruptedbysetting LD
LOW and toggling
WEN.
Note that the status of a partial flag (
PAEorPAF)outputisinvalidduring
the programming process. From the time parallel programming has begun, a
partial flag output will not be valid until the appropriate offset word has been
writtentotheregister(s)pertainingtothatflag.MeasuringfromtherisingWCLK
edge that achieves the above criteria;
PAF will be valid after two more rising
WCLK edges plus tPAF,
PAEwillbevalidafterthenexttworisingRCLKedges
plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when
LDissetLOWandRENissetLOW.DataarereadviaQnfromthe
Empty Offset Register on the first LOW-to-HIGH transition of RCLK. Upon the
second LOW-to-HIGH transition of RCLK, data are read from the Full Offset
Register. ThethirdtransitionofRCLKreads,onceagain,fromtheEmptyOffset
Register. See Figure 15, Parallel Read of Programmable Flag Registers, for
the timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writestotheFIFO. Theinterruptionisaccomplishedbydeasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading
oftheoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consistsofreadingoutthememorycontents,startingatthebeginningofmemory.
Retransmitsetupisinitiatedbyholding
RTLOWduringarisingRCLKedge.
REN and WEN must be HIGH before bringingRT LOW. Atleastoneword,
but no more than D - 2 words should have been written into the FIFO between
Reset (Master or Partial) and the time of Retransmit setup. D = 32,768 for the
IDT72V275 and D = 65,536 for the IDT72V285. In FWFT mode, D = 32,769
for the IDT72V275 and D= 65,537 for the IDT72V285.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmitsetupbysetting
EFLOW. Thechangeinlevelwillonlybenoticeable
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When
EFgoesHIGH,Retransmitsetupiscompleteandreadoperations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on
REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When
ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
the first word appears on the outputs, no LOW on
RENisnecessary.Reading
all subsequent words requires a LOW on
REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
For either IDT Standard mode or FWFT mode, updating of the
PAE, HF
and
PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after
RT is
setup, the
PAEflagwillbeupdated. HFisasynchronous,thustherisingedge
ofRCLKthat
RTissetupwillupdateHF. PAFissynchronizedtoWCLK,thus
thesecondrisingedgeofWCLKthatoccurstSKEWaftertherisingedgeofRCLK
that
RT is setup will update PAF. RT is synchronized to RCLK.
相关PDF资料 |
PDF描述 |
|---|---|
| 72V285L10PF8 | 64K X 18 OTHER FIFO, 6.5 ns, PQFP64 |
| 72V285L15TFI9 | 64K X 18 OTHER FIFO, 10 ns, PQFP64 |
| 72V3626L15PFG | 256 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 72V3684L15PF | 16K X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 72V845L15PFI8 | 4K X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 72V275L15PFG | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V275L15PFG8 | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V275L15PFGI | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V275L15PFGI8 | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度: 总线定向: 存储容量: 定时类型: 组织: 最大时钟频率: 访问时间: 电源电压-最大: 电源电压-最小: 最大工作电流: 最大工作温度: 封装 / 箱体: 封装: |
| 72V275L15PFI | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
发布紧急采购，3分钟左右您将得到回复。