7548 PDF资料下载(20/73 页)SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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参数资料

型号：	7548
厂商：	Renesas Technology Corp.
英文描述：	SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述：	单芯片8位CMOS微机
文件页数：	20/73页
文件大小：	1255K
代理商：	7548

Rev.2.00

REJ03B0210-0200

Mar 15, 2007

Page 20 of 70

7548 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Interrupts

Interrupts occur by 13 different sources : 5 external sources, 7

internal sources and 1 software source.

Interrupt control

All interrupts except the BRK instruction interrupt have an

interrupt request bit and an interrupt enable bit, and they are

controlled by the interrupt disable flag. When the interrupt

enable bit and the interrupt request bit are set to “1” and the

interrupt disable flag is set to “0”, an interrupt is accepted.

The interrupt request bit can be cleared by program but not be

set.

The interrupt enable bit can be set and cleared by program.

The reset and BRK instruction interrupt can never be disabled

with any flag or bit. All interrupts except these are disabled when

the interrupt disable flag is set.

When several interrupts occur at the same time, the interrupts are

received according to priority.

Interrupt operation

Upon acceptance of an interrupt the following operations are

automatically performed:

1.The processing being executed is stopped.

2.The contents of the program counter and processor status

3.The interrupt disable flag is set and the corresponding inter-

rupt request bit is cleared.

4.Concurrently with the push operation, the interrupt destina-

tion address is read from the vector table into the program

counter.

[Interrupt edge selection register] INTEDGE

The valid edge of external interrupt INT

and INT

can be

selected by the interrupt edge selection bit, respectively.

[Key-on wakeup input selection register] KEYS

Either of enable or disable of key-on wakeup for pins P1

to P1

can be selected by the key-on wakeup input selection bit,

respectively.

Fig 19. Structure of key-on wakeup input selection

Notes on use

(1) When setting the followings, the interrupt request bit may be

set to “1”.

When switching external interrupt active edge related register:

Interrupt edge selection register (address 003A

)

Capture mode register (address 0032

)

When not requiring the interrupt occurrence synchronized with

these setting, take the following sequence.

1.Set the corresponding interrupt enable bit to “0” (disabled).

2.Set the interrupt edge select bit (active edge switch bit, trig-

ger mode bit).

3.Set the corresponding interrupt request bit to “0” after 1 or

more instructions have been executed.

4.Set the corresponding interrupt enable bit to “1” (enabled).

Key-on wakeup input selection register

), initial value: 00

Port P1