- 您现在的位置：买卖IC网 > PDF目录294733 > 91C100FDREVB (SMSC Corporation) FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY PDF资料下载
参数资料
| 型号： | 91C100FDREVB |
| 厂商： | SMSC Corporation |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 宴快速以太网控制器以全双工能力 |
| 文件页数： | 31/68页 |
| 文件大小： | 423K |
| 代理商： | 91C100FDREVB |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
SMSC DS – LAN91C100FD REV. B
Page 37
Rev. 05/31/2000
TYPICAL FLOW OF EVENTS FOR TRANSMIT
S/W DRIVER
MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT
FOR
SUCCESSFUL
COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
5
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
6
Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO into
the TX completion FIFO. Interrupt is generated
by the TX completion FIFO being not empty.
7 SERVICE INTERRUPT - Read Interrupt Status
Register. If it is a transmit interrupt, read the TX
Done Packet Number from the Fifo Ports
Register. Write the packet number into the
Packet Number Register.
The corresponding
status word is now readable from memory. If
status word shows successful transmission,
issue RELEASE packet number command to
free up the memory used by this packet.
Remove packet number from completion FIFO
by writing TX INT Acknowledge Register.
相关PDF资料 |
PDF描述 |
|---|---|
| 91C94 | ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM |
| 92_TNC-50-0-4/111_NE | BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK |
| 92_TNC-50-0-4/111_NM | BOARD TERMINATED, FEMALE, TNC CONNECTOR, SURFACE MOUNT, JACK |
| 92082-314 | 14 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
| 92082-316 | 16 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 91C100GTQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 91C100QFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
| 91C15JC353 | 制造商:STM 功能描述:CGB015X335C |
| 91C1A-A24-A13/A15 | 制造商:BOURNS 制造商全称:Bourns Electronic Solutions 功能描述:91, 92, 93, 94, 95, 96 - 5/8 ” Square Single-Turn Panel Control 97, 99 - 5/8 ” Square Single-Turn Panel Control with Rotary Switch |
| 91C1A-A24-A13/A15L | 制造商:BOURNS 制造商全称:Bourns Electronic Solutions 功能描述:91, 92, 93, 94, 95, 96 - 5/8 ” Square Single-Turn Panel Control 97, 99 - 5/8 ” Square Single-Turn Panel Control with Rotary Switch |
发布紧急采购，3分钟左右您将得到回复。