参数资料
型号: 935262073551
厂商: NXP SEMICONDUCTORS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP64
封装: PLASTIC, QFP-64
文件页数: 10/43页
文件大小: 206K
代理商: 935262073551
2000 Feb 21
18
Philips Semiconductors
Product specication
Multiprotocol IC Card coupler
TDA8006
Table 9
UART Conguration Register (UCR; address 5; write only; all bits cleared after reset)
BIT
NAME
DESCRIPTION
D0
Reset ISO 7816 UART (RIUN); set by
software, reset by software
when LOW, this bit resets the UART; must be set by software
before any use of the UART
D1
Start Session (SS); set by software, reset by
software
when HIGH, this bit allows the detection of the convention
during the initial character of the card; must be reset by
software after correct reception of the rst character and before
complete reception of the next character
D2
Last Character to Transmit (LCT); set by
software, reset by hardware or software
when HIGH, this bit allows automatic toggling from transmission
to reception mode after successful transmission of the last
character; in this case, TRN is also reset by hardware
D3
Transmit/Receive-N (TRN); set by software,
reset by software or hardware
when LOW, the UART is in reception mode; when HIGH, it is in
transmission mode; INT goes LOW when TRN is set
D4
not used
D5
Protocol Selection (PS); set by software, reset
by software
when LOW, the UART is in T = 0 mode; when HIGH, the UART
is in T = 1 mode
D6
3 V/5 V-N (TFN); set by software, reset by
software
when LOW, the card supply voltage VCC = 5 V; when HIGH,
VCC =3V
D7
Synchrone/asynchrone-N (SAN); set by
software, reset by software
when HIGH, this bit allows direct monitoring of I/O by bit D0 of
SIR or SOR; when LOW, I/O is fed to the ISO 7816 UART
RECEPTION
In order to start a session with the card, bit RIUN (which
resets the ISO 7816 UART when LOW) must be set HIGH.
The UART recognizes the convention (direct or inverse) of
the characters received while bit SS (Start Session) is
HIGH. Then the UART automatically converts any
transmitted or received character according to this
convention, so the software only has to deal with
characters written in direct convention. Indeed, bit SS
must be reset by software after correct receipt of the first
character of the ATR (TS) and before complete receipt of
the next character.
Reception mode is selected when TRN is LOW. Bit FSD is
set within the UART Status Register (USR), and an
interrupt is generated, if enabled, at the start bit of the
received character when SS is HIGH, allowing the manual
CLK count during ATR. The interrupt will be cleared on the
rising edge of EN during the status read operation.
For the next characters, bit RBF is set at 10.5 ETU and an
interrupt is generated, if enabled, to indicate that a
character has been received, with or without parity error,
and that this character may be read within the reception
register. The interrupt is cleared on the falling edge of EN
during the read operation of the received character.
In protocol type T = 0 (bit PS LOW), the I/O line is
automatically pulled LOW between 10.5 and 11.75 ETU if
a character parity error is detected (parity error handling at
character level).
In protocol type T = 1 (bit PS HIGH), if a parity error is
detected, bit PE is set in the status register, but the I/O line
is not pulled LOW.
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