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| 型号： | 935262073551 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | PLASTIC, QFP-64 |
| 文件页数： | 7/43页 |
| 文件大小： | 206K |
| 代理商： | 935262073551 |
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2000 Feb 21
15
Philips Semiconductors
Product specication
Multiprotocol IC Card coupler
TDA8006
Table 5
Clock Conguration Register (CCR; address 0; write only; all bits cleared after reset)
X = don’t care.
D7
D6
D5
D4
D3
D2
D1
D0
UART
PRESCALER
CLK
CLKOUT
OSC
XXXXXXX
0
÷31
XXXXXXX
1
÷32
XXXX
0
X
STOP LOW
XXXX
0
1
X
1
2fxtal
XXXX
0
1
0
X
1
4fxtal
XXXX
0
1
X
1
8fxtal
XXXX
1
0
X
1
2fINT
XXXX
1
0
1
X
STOP HIGH
XX
0
XXXX
1
4fxtal
XX
0
1
XXXX
fxtal
XX
1
0
XXXX
1
2fxtal
0
XXXXXX
1
8fINT
0
1
XXXXXX
fxtal
1
0
XXXXXX
1
2fxtal
1
XXXXXX
1
2fINT
The hexadecimal value stored in the Programmable
Divider Register (PDR) is the auto-reload value of an 8-bit
counter clocked by the card clock (CLK); when the value is
loaded in the counter, it counts from this value till overflow;
then it is reloaded with the same value and the count
restarts. The output of the counter is then divided by
31 or 32 depending on the programmed value of the
UART prescaler. The result is the ISO 7816 UART CLK
which is used for shifting the data in or out on the I/O line.
The example shown in Fig.7 shows how to program a
division factor of 372. With these registers, the baud rates
given in Table 7 are achieved according to ISO 7816.
The division ratio of 31 or 32 depends on which prescaler
is selected, and the hexadecimal value is the value
programmed within the PDR.
Table 6
Programmable Divider Register (PDR; address 1; write only; all bits cleared after reset)
Note
1. A division factor of F4H, for example, would be 1111 0100 reading from D7 to D0.
D7
D6
D5
D4
D3
D2
D1
D0
DIVISION FACTOR
n7
n6
n5
n4
n3
n2
n1
n0
n7n6n5n4 n3n2n1n0(1)
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