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参数资料
| 型号： | 935267488112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 7.50 MM, PLASTIC, SO-20 |
| 文件页数： | 16/69页 |
| 文件大小： | 352K |
| 代理商： | 935267488112 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
21
BIT
SYMBOL
FUNCTION
I2CON.7
RDAT
Read: the most recently received data bit.
“
CXA
Write: clears the transmit active flag.
I2CON.6
ATN
Read: ATN = 1 if any of the flags DRDY, ARL, STP, or STP = 1.
“
IDLE
Write: in the I2C slave mode, writing a 1 to this bit causes the I2C hardware to ignore the bus until it
is needed again.
I2CON.5
DRDY
Read: Data Ready flag, set when there is a rising edge on SCL.
“
CDR
Write: writing a 1 to this bit clears the DRDY flag.
I2CON.4
ARL
Read: Arbitration Loss flag, set when arbitration is lost while in the transmit mode.
“
CARL
Write: writing a 1 to this bit clears the CARL flag.
I2CON.3
STR
Read: Start flag, set when a start condition is detected at a master or non-idle slave.
“
CSTR
Write: writing a 1 to this bit clears the STR flag.
I2CON.2
STP
Read: Stop flag, set when a stop condition is detected at a master or non-idle slave.
“
CSTP
Write: writing a 1 to this bit clears the STP flag.
I2CON.1
MASTER
Read: indicates whether this device is currently as bus master.
“
XSTR
Write: writing a 1 to this bit causes a repeated start condition to be generated.
I2CON.0
—
Read: undefined.
“
XSTP
Write: writing a 1 to this bit causes a stop condition to be generated.
* Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register should never be altered by
use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to the fact that read and write functions of this register
are different. Testing of I2CON bits via the JB and JNB instructions is supported.
—
SU01155
MASTER
STP
STR
ARL
DRDY
ATN
RDAT
0
1
2
3
4
5
6
7
I2CON
Reset Value: 81h
Bit Addressable*
Address: D8h
XSTP
XSTR
CSTP
CSTR
CARL
CDR
IDLE
CXA
READ
WRITE
Figure 9. I2C Control Register (I2CON)
BIT
SYMBOL
FUNCTION
I2DAT.7
RDAT
Read: the most recently received data bit, captured from SDA at every rising edge of SCL. Reading
I2DAT also clears DRDY and the Transmit Active state.
“
XDAT
Write: sets the data for the next transmitted bit. Writing I2DAT also clears DRDY and sets the
Transmit Active state.
I2DAT.6–0
–
Unused.
—
SU01156
—
RDAT
0
1
2
3
4
5
6
7
I2DAT
Reset Value: xxh
Not Bit Addressable
Address: D9h
—
XDAT
READ
WRITE
Figure 10. I2C Data Register (I2DAT)
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