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参数资料
| 型号： | 935267488112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 7.50 MM, PLASTIC, SO-20 |
| 文件页数： | 2/69页 |
| 文件大小： | 352K |
| 代理商： | 935267488112 |
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Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
8
Name
Reset
Value
Bit Functions and Addresses
MSB
LSB
SFR
Address
Description
KBI#
Keyboard Interrupt
86h
00h
87
86
85
84
83
82
81
80
P0*
Port 0
80h
T1
CMP1
CMPREF
CIN1A
CIN1B
CIN2A
CIN2B
CMP2
Note 2
97
96
95
94
93
92
91
90
P1*
Port 1
90h
(P1.7)
(P1.6)
RST
INT1
INT0
T0
RxD
TxD
Note 2
A7
A6
A5
A4
A3
A2
A1
A0
P2*
Port 2
A0h
–
X1
X2
Note 2
P0M1#
Port 0 output mode 1
84h
(P0M1.7)
(P0M1.6)
(P0M1.5)
(P0M1.4)
(P0M1.3)
(P0M1.2)
(P0M1.1)
(P0M1.0)
00h
P0M2#
Port 0 output mode 2
85h
(P0M2.7)
(P0M2.6)
(P0M2.5)
(P0M2.4)
(P0M2.3)
(P0M2.2)
(P0M2.1)
(P0M2.0)
00H
P1M1#
Port 1 output mode 1
91h
(P1M1.7)
(P1M1.6)
–
(P1M1.4)
–
(P1M1.1)
(P1M1.0)
00h1
P1M2#
Port 1 output mode 2
92h
(P1M2.7)
(P1M2.6)
–
(P1M2.4)
–
(P1M2.1)
(P1M2.0)
00h1
P2M1#
Port 2 output mode 1
A4h
P2S
P1S
P0S
ENCLK
T1OE
T0OE
(P2M1.1)
(P2M1.0)
00h
P2M2#
Port 2 output mode 2
A5h
–
(P2M2.1)
(P2M2.0)
00h1
PCON
Power control register
87h
SMOD1
SMOD0
BOF
POF
GF1
GF0
PD
IDL
Note 3
D7
D6
D5
D4
D3
D2
D1
D0
PSW*
Program status word
D0h
CY
AC
F0
RS1
RS0
OV
F1
P
00h
PT0AD#
Port 0 digital input disable
F6h
00h
9F
9E
9D
9C
9B
9A
99
98
PWMCON0
PWM Control Register 0
DAh
RUN
XFER
PWM3I
PWM2I
–
PWM1I
PWM0I
–
00h
PWMCON1
PWM Control Register 1
DBh
BKCH
BKPS
BPEN
BKEN
PWM3B
PWM2B
PWM1B
PWM0B
00h
SCON*
Serial port control
98h
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00h
SBUF
Serial port data buffer
register
99h
xxh
SADDR#
Serial port address register
A9h
00h
SADEN#
Serial port address enable
B9h
00h
SP
Stack pointer
81h
07h
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 control
88h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
TH0
Timer 0 high byte
8Ch
00h
TH1
Timer 1 high byte
8Dh
00h
TL0
Timer 0 low byte
8Ah
00h
TL1
Timer 1 low byte
8Bh
00h
TMOD
Timer 0 and 1 mode
89h
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00h
WDCON#
Watchdog control register
A7h
–
WDOVF
WDRUN
WDCLK
WDS2
WDS1
WDS0
Note 4
WDRST#
Watchdog reset register
A6h
xxh
NOTES:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset value shown in the table for these bits is 0.
2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte.
3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon
power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up.
4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00
0000b for all other reset causes if the watchdog is disabled.
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