- 您现在的位置：买卖IC网 > PDF目录122717 > 935267488112 (NXP SEMICONDUCTORS) 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 PDF资料下载
参数资料
| 型号： | 935267488112 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 7.50 MM, PLASTIC, SO-20 |
| 文件页数： | 9/69页 |
| 文件大小： | 352K |
| 代理商： | 935267488112 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
Philips Semiconductors
Preliminary specification
87LPC768
Low power, low price, low pin count (20 pin) microcontroller with
4 kB OTP 8-bit A/D, Pulse Width Modulator
2000 May 02
15
Internal Reference Voltage
An internal reference voltage generator may supply a default
reference when a single comparator input pin is used. The value of
the internal reference voltage, referred to as Vref, is 1.28 V ±10%.
Comparator Interrupt
Each comparator has an interrupt flag CMFn contained in its
configuration register. This flag is set whenever the comparator
output changes state. The flag may be polled by software or may be
used to generate an interrupt. The interrupt will be generated when
the corresponding enable bit ECn in the IEN1 register is set and the
interrupt system is enabled via the EA bit in the IEN0 register.
Comparators and Power Reduction Modes
Either or both comparators may remain enabled when Power Down
or Idle mode is activated. The comparators will continue to function
in the power reduction mode. If a comparator interrupt is enabled, a
change of the comparator output state will generate an interrupt and
wake up the processor. If the comparator output to a pin is enabled,
the pin should be configured in the push-pull mode in order to obtain
fast switching times while in power down mode. The reason is that
with the oscillator stopped, the temporary strong pull-up that
normally occurs during switching on a quasi-bidirectional port pin
does not take place.
Comparators consume power in Power Down and Idle modes, as
well as in the normal operating mode. This fact should be taken into
account when system power consumption is an issue.
Comparator Configuration Example
The code shown in Figure 7 is an example of initializing one
comparator. Comparator 1 is configured to use the CIN1A and
CMPREF inputs, outputs the comparator result to the CMP1 pin,
and generates an interrupt when the comparator output changes.
The interrupt routine used for the comparator must clear the
interrupt flag (CMF1 in this case) before returning.
SU01189
CmpInit:
mov
PT0AD,#30h
; Disable digital inputs on pins that are used
;
for analog functions: CIN1A, CMPREF.
anl
P0M2,#0cfh
; Disable digital outputs on pins that are used
orl
P0M1,#30h
;
for analog functions: CIN1A, CMPREF.
mov
CMP1,#24h
; Turn on comparator 1 and set up for:
;
– Positive input on CIN1A.
;
– Negative input from CMPREF pin.
;
– Output to CMP1 pin enabled.
call
delay10us
; The comparator has to start up for at
;
least 10 microseconds before use.
anl
CMP1,#0feh
; Clear comparator 1 interrupt flag.
setb
EC1
; Enable the comparator 1 interrupt. The
;
priority is left at the current value.
setb
EA
; Enable the interrupt system (if needed).
ret
; Return to caller.
Figure 7.
Pulse Width Modulator
The 87LPC768 contains four Pulse Width Modulated (PWM)
channels which generate pulses of programmable length and
interval. The output for PWM0 is on P0.1, PWM1 on P1.6, PWM2
on P1.7 and PWM3 on P0.1. After chip reset the internal output of
the each PWM channel is a “1.” Note that the state of the pin will
not reflect this if UCFG1.5, PRHI, is set to a zero. In this case
before the pin will reflect the state of the internal PWM output a “1”
must be written to each port bit that serves as a PWM output. A
block diagram is shown in Figure 8.
The interval between successive outputs is controlled by a 10–bit
down counter which uses the internal microcontroller clock as its
input. When bit 3 in the UCFG1 register is a “1” the microcontroller
clock, and therefore the PWM counter clock, has the same
frequency as the clock source defined by the FOSC bits in UCFG1.
When bit 3 in the UCFG1 register is a “0” the microcontroller and
PWM counter clocks operate at half the frequency of clock source
defined by the FOSC bits in UCFG1. When the counter reaches
underflow it is reloaded with a user selectable value. This
mechanism allows the user to set the PWM frequency at any integer
sub–multiple of the microcontroller clock frequency. The repetition
frequency of the PWM is given by:
fPWM = FC / (CNSW+1)
where CNSW is contained in CNSW0 and CNSW1 as described in
the following tables.
相关PDF资料 |
PDF描述 |
|---|---|
| 9ERS3165BGILF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 9LPRS535BFLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 935208500112 | 8-BIT, 16 MHz, MICROCONTROLLER, PDIP40 |
| 935208540112 | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44 |
| 935267591518 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
| 935269544557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-2US1-V1.3 |
| 935269987557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY TDA9587-1US1-V1.8 SUBBED TO 935269987557 |
发布紧急采购，3分钟左右您将得到回复。